“射频电路设计的关键技术和技巧”专题讲座讲义3

1、 Lecture 2 : Voltage and Power Transportation Richard Chi-Hsi Li 李缉熙 Email : 1. Voltage Delivered from a Source to a Load o General Expression of Voltage Delivered from a Source to a Load o Additional jitter or Distortion in a Digital Circuit Block 2. Power Delivered from a Source to a Load o Genera

2、l Expression of Power Delivered from a Source to a Load o Power Instability o Additional Power Loss o Additional Distortion o Additional interference3. Impedance Conjugate Matching o Maximization of Power Transportation o Power Transportation without Phase Shift o Impedance Matching Network o Necess

3、ity of Impedance Matching 4. Additional Effect of Impedance Matching o Voltage Pumped up by Impedance Matching o Power MeasurementLecture 211. Voltage delivered from a source to a loado General expression of voltage delivered from source to load Figure 1 Voltage delivered from a source to a loadSLZo

4、RSXS ZSSourcePSvS XL ZLLoadRLLecture 22tl (Delay time =Td) SourceLoadFigure 2 Voltages bouncing back and forth arrive at load when t =Td . Note: kv = RL/(ZS+ZL)Voltage delivered from Source:Voltage delivered from Source:-12Td -11Td Voltage delivered from Source:Voltage delivered from Source:-10Td -9

5、Td -8Td 2Td 1Td -1Td 0 -3Td -2Td -5Td -4Td -7Td -6Td Voltage delivered from Source:Voltage delivered from source: Voltage delivered from Source:Voltage arrived at RL ,Lecture 23Lecture 24 , o Additional Jitter or Distortion in a Digital Circuit BlockLecture 25Table 1 Additional distortion and additi

6、onal jitter in voltage transportation when f = 3.86 GHz S, %L, % D,% f, GHz T, ns Jitter, % Jitter, ps00 3.86 0.2590.00 050 3.860.2590.00 0100 3.860.2590.00 0200 3.860.2590.00 0500 3.860.2590.00 0053.860.2590.00 0553.860.2591053.860.259 2053.860.2595053.860.2590103.860.2590.00 05103.860.259 10103.86

7、0.25920103.860.25950103.860.259 0203.860.259 0.00 05203.860.25910203.860.25920203.860.25950203.860.2590503.860.2590.00 05503.860.25910503.860.25920503.860.25950503.860.259Lecture 26 , and then,1) when , and then,2) when , and then,3) when The voltage reflection becomes pernicious. The voltage reflec

8、tion seems not too harmful. The voltage reflection is horrible!Lecture 272. Power delivered from a source to a loado General expression of power delivered from source to loadFigure 2 Power delivered from a source to a loadSLZoRSXS ZSSourcePSvS XL ZLLoadRLLecture 28tl (Delay time =Td) SourceLoadFigur

9、e 4 Powers bounce forth and back and arrive at load when t =Td . (Note: kp=RL/|ZS+ZL|2)Power delivered from source:Power delivered from source:-12Td -11Td Power delivered from source:Power delivered from source:-10Td -9Td -8Td 2Td 1Td -1Td 0 -3Td -2Td -5Td -4Td -7Td -6Td Power delivered from source:

10、Power delivered from source:Power delivered from source:Power arrived at RL ,Lecture 29o Power InstabilityLecture 210o Additional Power LossLecture 211 Table 2 Additional power loss due to the unmatched case when = -30 dBm.S, %L, % ,dBm ,dBm ,dBm000.0000 -30-infinite-30500.0000 -30 -infinite-301000.

11、0000-30 -infinite-302000.0000-30-infinite-305000.0000-30 -infinite-30050.0500-30 -43.01-30.22550.0476 -30 -43.22-30.211050.0452-30-43.45-30.202050.0404-30-43.94-30.185050.0256 -30-45.91-30.110100.1000 -30 -40.00-30.465100.0955 -30 -40.20-30.4410100.0909-30-40.41-30.4120100.0816 -30 -40.88-30.3750100

12、.0526-30-49.79-30.230200.2000-30-36.99-30.975200.1919-30-37.17-30.9310200.1837 -30-37.36-30.8820200.1667 -30-37.78-30.7950200.1111-30-354-30.510500.5000-30-33.01-33.015500.4872-30-33.12-39.9010500.4737-30-33.25-39.7920500.4444-30-33.52-39.5550500.3333-30-34.77-31.76Lecture 212o Additional Distortion

13、Lecture 213Table 3 Additional distortion in power transportation S, % L, % Dp,% 000.00 500.00 1000.00 2000.00 5000.00 0529.365521.8210521.2720520.1050516.0101031.6251030.90101030.15201028.57501029.9402044.7252043.81102049.86202040.82502033.3305070.7155068.00105068.82205066.67505057.74 Lecture 214Fro

14、m Table 3 it can be seen that In cases where L = 0, there is no additional distortion. On the contrary, in the cases of L 0, the additional distortion is appreciable! The additional distortion is more sensitive to the value of L than to the value of S, For given value of L, the additional distortion

15、 is somewhat reduced as the value of S is increased. For given value of S, the additional distortion is somewhat increased as the value of L is increased. The highest value of the additional distortion in Table 9.3 is 70.71% when S=0 and L =50%.Lecture 215o Additional InterferenceLecture 216 Table 4

16、 Calculated ratio of signal to interference as the reflection coefficient, , is varied.S, L,% % dB W % W W dB0015 31.620.00000.00001.0015.005015 31.62 0.00000.00001.0015.0010015 31.620.00000.00001.0015.0020015 31.620.00000.00001.0015.0050015 31.62 0.00000.00001.0015.000515 31.620.00000.00001.0015.00

17、5515 31.620.00250.00251.0814.6710515 31.620.00500.00501.1614.3620515 31.620.01000.01011.3213.8050515 31.620.02500.02561.8112.4201015 31.620.00000.00001.0015.0051015 31.620.00500.00501.1614.36101015 31.620.01000.01011.3213.80201015 31.620.02000.02041.6512.84501015 31.620.05000.05262.6610.7402015 31.6

18、20.00000.00001.0015.0052015 31.620.01000.01011.3213.80102015 31.620.02000.02041.6512.84202015 31.620.04000.04172.3211.35502015 31.620.10000.11114.51 8.4505015 31.620.00000.00001.0015.0055015 31.620.02500.02561.8112.42105015 31.620.05000.05262.6610.74205015 31.620.10000.11114.51 8.45505015 31.620.250

19、00.333311.54 4.38Lecture 217From Table 4 it can be seen that In cases where L = 0, there is no additional interference, so the SIR is kept unchanged. The additional interference is more sensitive to the value of L than to the value of S, For a given value of L, the additional interference increases

20、as the value of S increases so that the SIR is reduced. For a given value of S, the additional interference increases as the value of L increases so that the SIR is reduced. The highest value of the additional interference in Table 9.4 is reached when S=50% and L=50%. At this point the SIR drops fro

21、m 15 dB to 4.38 dB.Lecture 218 o Maximizing of Power Transportation , or, , or , or, 3. Impedance Conjugate MatchingFigure 5 Power delivered from a source to a load without reflectionS= 0L= 0ZoRSXS ZSSourcePSvS XL ZLLoadRLLecture 219This is called “neutralization of reactance between source and load

22、. o Power Transportation without Phase Shift Figure 6 Two matching cases when reactance of source is “neutralized” by reactance of load, or, vice versa, that is, XS = -XL(a) RS in series with XS (b) RS in parallel with XS RL in series with XL RL in parallel with XLRSRLvS vLXSXL“Neutralization”of rea

23、ctanceRSRLvL XLXS“Neutralization”of reactancevS Lecture 220(c) 8PSK(b) 4PSK(a) BPSK(e) 16QAM(f) 64QAM9.46oFigure 7 Progress of modulation technology from PSK to QAM(d) 16PSK22.5o26.56oLecture 221Lecture 222 A matching network must be inserted between source and load so that the impedance matching co

24、ndition can be satisfied as following :o Impedance Matching NetworkUsuallyRSvSXSSourcePSXLRLLoadFigure 8 An impedance matching network is inserted between source and load when ZS ZL* Impedance MatchingNetworkZinZoutZSZLPinPoutLecture 223XLRLOld LoadRSvSXSOld SourcePSFigure 9 First sub- impedance mat

25、ching loop: *New source = old source, *New load = Impedance matching network + old load Impedance Matching NetworkZinZoutZSZLPinPoutNew Source=Old sourceXinRinNew load=Impedance matching network +old loadvinLecture 224Figure 10 Second sub- impedance matching loop: the impedance matching network itse

26、lf Impedance MatchingNetworkZinZoutPinPoutRinXinRoutXoutLecture 225RSvSXSOld SourcePSXLRLOld LoadFigure 11 Third sub-impedance matching loop: *New source = Old source+ Impedance matching network *New load = Old load Impedance Matching NetworkZinZoutZSZLPinPoutNew load=Old loadXoutRoutNew source= old

27、 source + Impedance matching network Lecture 226RSvSXSSourcePSXLRLLoadFigure 8 An impedance matching network is inserted between source and load when ZS ZL* Impedance MatchingNetworkZinZoutZSZLPinPoutLecture 227o Necessity of Impedance MatchingIs this impedance matching network necessary ?Figure 12

28、A source follower (DC bias is neglected)VddInRoOutVddInRoImpedanceMatching Network OutZx(a) Primary source follower(b) “Improved” source follower?Is it necessary to insert an impedance matching network between two parts (Inductor, capacitor, resistor) ?Lecture 228(a) A primary MOSFET cascode amplifi

29、erCZeroBias 1Bias 2VddOutRF chokeRF chokeInRdM1M2Figure 13 A MOSFET cascode amplifier(b) An impedance matching network inserted between two stagesCZeroBias 1Bias 2VddOutRF chokeRF chokeInRdM1M2ImpedanceMatching NetworkIs this impedance matching network necessary ?Lecture 2294. Additional effects of

30、impedance matchingZLO = 3.35 j105.5 in seriesZLO = 3.325k / 0.39pF in parallelFigure 14 Conversion of impedance at LO port of a mixer (f = 3.86 GHz)LOZLOLOZLODevice0.39 pF3.325 LOZLODevice3.325 ZLO 3.325k, if 0.39 pF is neutralized. (Measured) Is it necessary to match LO portion ? Some engineers des

31、ign mixer without matching of LO portion. The reasons are Instead of power, only voltage is needed to ON/OFF the devices.As long as the runner from LO source to LO injection gate is short enough, the voltage from source would be directly effective on the gate.Or, one can simply put a 50 on LO inject

32、ion gate for matching to 50 source.o Voltage Pumped Up by Impedance MatchingLecture 230Rs=50 vgDevicevsVRs=50 DevicevgRs=50 Rg=50 vgDevicevsVvsVMatchingNetworkRs=50 vgDeviceRL=3.325 kRs=50 RL=3.325 kDevicevgvs=VRs=50 Rg=50 vgDeviceRL=3.325 kvs=VvsV(a) At LO port, the impedance matching is ignored.(b

33、) At LO port, a 50 resistor is connected in parallelAt LO port, impedance is well-matched by inserting of a matching network between the LO injection source and the LO injection port.)MatchingNetworkPs=0 dBmPs=0 dBmPs=0 dBmPs=0 dBmPs=0 dBmPs=0 dBmPg= -3 dBmLO portEquivalent circuitFigure 15 Three di

34、fferent ways for impedance matching at the LO port of a mixerLecture 231by power meter or spectrum analyzero Additional effects of impedance matching* Power MeasurementFigure 16 Output power of a tested block is measured by a power meter or a spectrum analyzer.PPEquivalentTested circuitvSZS*50 ZSPow

35、er meterOrSpectrum AnalyzerMatchNetwork(ZS* to 50 ohms)(a) Matched caseEquivalentTested circuitvSPL50 ZSPower meterOrSpectrum Analyzer(b) Un-matched case PL50 Lecture 232* Power Measurement by spectrum analyzer (Matched case)(a) Matched caseTested BlockvSZS*vL, PL50 ZSSpectrumAnalyzerMatchNetwork(ZS

36、* to 50 )Figure 17 Power measurement by spectrum analyzerLecture 233* Power Measurement by spectrum analyzer (Un-matched case)RS,XS PL/PoPL/Po, (ohms)(ohms) (dB) (b) Un-matched case Tested BlockvSvL, PL50 ohmsZSspectrum AnalyzerFigure 18 Power measurement by spectrum analyzerTable 5 Calculated value

37、s of PL/Po in un-matched case (b)Lecture 234 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 10 100 1000 10000XS , P*/P, dB0-10-20-30-40-50RS =10 RS =50 RS =100 RS =1000 RS =10000 Figure 20 Plot of calculated power ratio, PL*/Po , vs. impedance of DTU, ZS.Impedance of power meter or others = 50 Lect

38、ure 235o Burning of the deviceHigh Power PARSVSiRLLZoutZinFigure 19 Possible burning of devices in the bench work for a PA.Lecture 236Voltage Standing Wave Ratio in dB: Appendix A VSWR and Other Reflection and Transmission CoefficientsPower reflection coefficient:Transmitted power in %:Reflected pow

39、er in %:Transmission loss in dB:Return loss in dB:Voltage reflection coefficient:Voltage Standing Wave Ratio:Note : r= R/Ro, Ro = 50 ohmLecture 237Table A.1 Relationships between impedance, reflection coefficient, transmission coefficient, and other parameters along with the axis U(V=0) in the compl

40、ex plane of voltage reflection coefficient R,(Ro = 50)r=R/Ro|VSWRVSWRdB (S11 or S22)RLdBTLdB PT,%PR,% 14.00660.28010.563.5711.06-5.000-1.65090.3268.3631.64 Lecture 238关于举办“射频电路设计的关键技术和技巧专题讲座的邀请函各有关单位： 为了促进我国射频电路应用设计产业的开展，提高射频电路设计水平和能力，学习和借鉴国外的先进技术和经验，中国电子电器可靠性工程协会决定组织召开第六期“射频电路设计的关键技术和技巧专题讲座。讲座将聘实战经

41、验丰富的资深美籍华人专家讲解射频电路应用设计技术和经验。具体事宜通知如下：一、课程特色讨论和強调射频电路设计的根本技术和技巧; 譬如,阻抗匹配,射频接地, 单端线路和差分线路之間的主要差別, 射频集成电路设计中的难题可以把它归类为橫向论述. 到目前为止，这种着重于设计技巧的論述是前所未有的，也是很独特的。讲演者认为，作为一位合格的射频电路设计的设计者，不管是工程师，还是教授，应当掌握这一局部所论述的根本的设计技术和技巧, 包括：阻抗匹配；接地；射频集成电路设计；6 Sigma 设计。二、学习目标：在本讲座结束之后， 学员可以了解到：o比照数码电路，射頻电路设计的主要差別是什麼? o什么是射频设

42、计中的根本概念?o在射频电路设计中如何做好窄带的阻抗匹配？o在射频电路设计中如何做好宽带的阻抗匹配？o在射频线路板上如何做好射频接地的工作?o为什么在射频和射频集成电路设计中有从单端至双差分的趋势?o为什么在射频电路设计中容许误差分析如此重要?o什么是射频和射频集成电路设计中的主要难题？射频和射频集成电路设计师如何克服这些障碍?Lecture 239三、课程提纲：讲课内容届时根据实际情况会有所调整。 第一讲 射频和数字电路的不同设计方法1.争论阻抗匹配关键参数线路测试和主要测试设备 在通讯系统中射频和数字方块的差异阻抗电流 方块位置结论给高速数字电路设计提点意见 第二讲 电压和功率传输1从源发

43、送电压至负载2从源发送电压至负载的一般表达式在数字电路方块中的附加Jitter 或畸变。从源发送电压至负载的一般表达式功率的不稳定性 附加的功率损失附加畸变附加干扰阻抗共轭匹配2.3.最大的功率传输无相移的功率传输阻抗匹配网络 阻抗匹配的必要性 阻抗匹配的附加效应借助于阻抗匹配来抬高电压功率测量；附录：2A.1电压驻波比VSWR 和其他反射及传输系数；2A.2功率 (dBm), 电压 (V), 和功率(Watt)之间的关系；第三讲 在窄带情况下的阻抗匹配引言借助于返回损失的调整进行阻抗匹配在Smith图上的返回损失圆返回损失和阻抗匹配的关系阻抗匹配网络的建造 一个零件的阻抗匹配网络在阻抗匹配网

44、络串接一个零件 在阻抗匹配网络并接一个零件两个零件的阻抗匹配网络在Smith图上的区域划分零件的数值线路的选择三个零件的阻抗匹配网络3.5.1“ and “T 型的匹配网络推荐的匹配网络线路当 ZS 或 ZL 不是50 的阻抗匹配阻抗匹配网络的零件附录：1Smith 图的根底知识 2两个零件阻抗匹配网络的公式3两个零件阻抗匹配网络的线路限制4三个零件阻抗匹配网络的线路限制5在 “ 和“T 型的匹配网络之间的转换6可能的 “ 和 “T 型的匹配网络第四讲 在宽带情况下的阻抗匹配 宽窄带返回损失在Smith图上的表现。接上每臂或每分支含有一个零件之后阻抗的变化在阻抗匹配网络串接一个电容在阻抗匹配网

45、络串接一个电感在阻抗匹配网络并接一个电容在阻抗匹配网络串接一个电感接上每臂或每分支含有两个零件之后阻抗的变化两个零件串接在一起形成一臂 4.3.2两个零件并接在一起形成一分支超宽带系统IQ 调制器 设计的阻抗匹配在IQ 调制器中的Gilbert Cell 。4.4.2Gilbert Cell的阻抗不考量带宽在LO, RF and IF 终端的阻抗匹配超宽带系统对带宽的要求。4.4.5扩展带宽的根本思路。第一个例子: 在超宽带系统第一组IQ 调制器设计中的阻抗匹配第二个例子: 在超宽带系统第三和第六组IQ 调制器设计中的阻抗匹配4.5Discussion of Wide-band Impedance Matching Network4.5.1MOSFET 管子栅极的阻抗匹配4.5.2MOSFET 管子漏极的阻抗匹配第六讲阻抗测量 ：引言标量和矢量的电压测量 示波器的电压测量矢量电压计的电压测量用网络分析仪直接测量阻抗 阻抗测量的方向性6.3.2S 参数测量的好处6.3.3S 参数阻抗测量的理论背景用矢量电压计测量S 参数网络分析仪的校准借助于网络分析仪的另一种阻抗测量6.4.1Smith 图的精度上下阻抗的测量借助于循环器的阻抗测量附录：阻抗串并联接之间的关系第七讲：接地：接地的涵义在线路图中可能隐