eda技术实用教程习题答案

1、EDA (第四版)题关系？FPGA ASIC 1习EDA ASIC FPGA 用与特点综合?有哪些类型?综合在电子设计自动化中的地位是什么在EDA 技术中，自顶向下的设计方法的重要意义是什么?IP 在EDA 技术的应用和发展中的意义是什么?EDA (第四版)题关系？FPGA ASIC 1习EDA ASIC FPGA 用与特点综合?有哪些类型?综合在电子设计自动化中的地位是什么在EDA 技术中，自顶向下的设计方法的重要意义是什么?IP 在EDA 技术的应用和发展中的意义是什么?EDA FPGA/CPLD EDA 2习题OLMC（输出逻辑宏单元）有何功能?GAL 电路的。 基于乘积项的可编程逻辑结

2、构辑结构FPGA系列器件中的LAB有何作用解释编程与配置这两个概念。 辑结构的 PLD 器件归类为 CPLD；将基于查找表的可编程逻辑结构的 PLD XPLD器件? MAX IIPLD件?为什么3习题ENTITYbuf3s enable:IN STD_LOGIC; output:OUTSTD_LOGIC);ENDbuf3s ENTITYmux21 2选1 多路选择INoutput:OUT3-2 3-16 4 1 多路选择器,IF_THEN CASE 语句的表达方VHDL 程序,s1 s0 STD_LOGIC_VECTOR;3-2 3-16 4 1 多路选择器,IF_THEN CASE 语句的表

3、达方VHDL 程序,s1 s0 STD_LOGIC_VECTOR;4选1 多路选择-1IF_THEN41ENTITY mux41 IS(a,b,c,d:ININSTD_LOGIC; INOUTENDENTITYOFSIGNALs0s1STD_LOGIC_VECTOR(1DOWNTO0);-定义标准逻辑 -s1s0,s1s0s0s1=s0s1=s0s1=yENDEND-2CASE41 ENTITY mux41 IS(a,b,c,d:ININSTD_LOGIC; INOUTENDENTITYOFENTITY mux41 IS(a,b,c,d:ININSTD_LOGIC; INOUTENDENTIT

4、YOFSIGNALs0s1STD_LOGIC_VECTOR(1DOWNTO0);-定义标准逻辑 -s1s0,s1s0 CASEs0s1WHENWHENWHENWHEN-caseyWHENENDENDEND图3-1721CASE21MUX21A含2选1 多路选择器的模-CASE4-1821 ENTITY mux31 ISPORT(a1,a2,a3,s0,s1:INouty:OUTSTD_LOGIC); END ENTITY mux31;OFSIGNALy:CASEs0WHENWHEN-caseWHENCASEs0WHENWHEN-caseWHENENDENDCASEs1WHENWHEN-case

5、WHENENDENDEND RSTLOAD改为异步控制方式。-VHDLUSEUSEIEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT12 ISPORT(CLK,RST,EN,LOAD:IN3-20 3-21 :INSTD_LOGIC_VECTOR(3DOWNTO0);4DOUTOUTSTD_LOGIC_VECTOR(3DOWNTO0);-COUT:OUTSTD_LOGIC); END CNT12;ARCHITECTUREbehavOFCNT12Q:STD_LOGIC_VECTOR(3DOWNTOREG:IFLOAD=0THENELSIFCLKEVENTANDCLK=

6、1IFRST=0THENQ0);IFEN=1IFQ12THENELSEQ0); END IF;ENDIF; END IF;ENDEND-9END PRO COM:IFQ=12THENCOUT=19，输出进位信号 ELSE COUT=0;ENDELSEQ0); END IF;ENDIF; END IF;ENDEND-9END PRO COM:IFQ=12THENCOUT=19，输出进位信号 ELSE COUT ENDIFF#THEN ELSECOUT0 THENELSE CQI:=(OTHERS = 1);ENDIFCQI=0THENCOUT=1; ELSE COUT = 0;ENDIF; EN

7、D IF;ENDENDIFCQI=0THENCOUT=1; ELSE COUT = 0;ENDIF; END IF;ENDEND3-18D 触发器的时序电路(sxdl),-4-19VHDLt4_19.vhd LIBRARYIEEE;ENTITY t4_19 IS(CL,CLK0: IN STD_LOGIC; OUTSTD_LOGIC);ENDENTITYOF t4_19SIGNAL Q : STD_LOGIC;CLK0EVENT AND CLK0=1Q = NOT(Q OR CL);ENDENDOUT1=NOTEND1VHDL8位全减器。要求1)1位半减器,然后用例化语句将它们连接起来,4-2

8、0中h_suber是半减器,diffa输出差(diff=x-y),s_out是借位输出b1位全加-解(1.1)1h_suber(diff=x-USEENTITYh_suber INdiff,s_out: OUT STD_LOGIC); END ENTITY-解(1.1)1h_suber(diff=x-USEENTITYh_suber INdiff,s_out: OUT STD_LOGIC); END ENTITYOFh_suberIS =xXOR (NOTs_out sub_in,sub_outx1,yin=y1,diff_out=diff1,sub_in=a0,sub_out=a1); OR

9、TMAP(xin=x2,yin=y2,diff_out=diff2,sub_in=a1,sub_out=a2); ORTMAP(xin=x3,yin=y3,diff_out=diff3,sub_in=a2,sub_out=a3); ORTMAP(xin=x4,yin=y4,diff_out=diff4,sub_in=a3,sub_out=a4); ORTMAP(xin=x5,yin=y5,diff_out=diff5,sub_in=a4,sub_out=a5); ORTMAP(xin=x6,yin=y6,diff_out=diff6,sub_in=a5,sub_out=a6);ENDARCHI

10、TECTURE41VHDL描述。选通控制端有四个输入：S0、S1、S2S3S0=0时:Y=A；S1=0时:Y=B；S2=0时:Y=C；S3=0时:Y=D-解：41VHDL -3-20(c)RTLVHDL8 USEENTITYmux41a A,B,C,DINS0,S1,S2,S3INUSEENTITYmux41a A,B,C,DINS0,S1,S2,S3INY:OUTSTD_LOGIC); END ENTITY mux41a;ARCHITECTUREoneOFmux41aSIGNALS0_3:STD_LOGIC_VECTOR(3DOWNTO0); WHENS0_3=0111ELSE WHENS0

11、_3=1011ELSE WHENS0_3=1101WHENS0_3=1110ENDARCHITECTURE3-9 分频方法有多种，最简单的是二分频和偶数分频甚至奇数分频，这用触发器或指定试对例 3-20 的设计稍作修改，将其进位输出 COUT 与异步加载控制 LOAD 连在一起，16 16 VHDL表述，并说明工作原理。设输入频率 fi=4MHz，输出频率 fo=516.51Hz(允许误差0.1Hz)， 16 位加载数值是多少?16位数控分频器(可进行奇偶数分频) LIBRARYIEEE;USEUSEIEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DVF16 ISINI

12、NSTD_LOGIC_VECTOR(15DOWNTO0); : OUT STD_LOGIC);END ENTITY DVF16; ARCHITECTUREoneOFDVF16IS SIGNAL FULL : STD_LOGIC;P_REG:VARIABLECNT8:STD_LOGIC_VECTOR(15DOWNTO0); IFCLKEVENTAND CLK=1IFCNT8=0000000000000000CNT8T8计数归0时，预置CNT8=D-计数范围(D=n)：n-1n/2取整(n=10:98765计数,前后半周期相同FULL1;-FULL ELSIFCNT8=(0&D(15DOWNTO1

13、)CNT8:=(0&D(15DOWNTO当T8=n/2ELSIFCNT8=(0&D(15DOWNTO1)CNT8:=(0&D(15DOWNTO当T8=n/2CNT8=D/2取整-计数范围(D=n)：n/2取整0(n=10:43210计数FULL1FULLELSECNT8CNT8-1 FULL=0; END IF;ENDENDSP_REG-FULLVARIABLECNT2:STD_LOGIC; IFFULLEVENTANDFULL=1CNT2NOTCNT2;-FULLIF CNT2 = 1 THENFOUT=1; ELSE FOUT 0); ELSIFCLKEVENTANDCLK=1THENIF

14、EN=1IFQ0);9ENDENDENDENDIFQ=9THENCOUT=1;9，输出进位信号 ELSE COUT=0;ENDEND PROENDENDENDENDENDIFQ=9THENCOUT=1;9，输出进位信号 ELSE COUT ENDIFF#THEN ELSECOUT0ELSECQI:=(OTHERS= ENDIFCQI=0THENCOUT=1; ELSE COUT = 0;ENDIF; END IF;ENDENDIFCQI=0THENCOUT=1; ELSE COUT = 0;ENDIF; END IF;ENDEND3-20RTLVHDLD触发器和锁存RTLRTL图-3-20(a

15、)RTLVHDLt3_12_a.vhd LIBRARYIEEE;ENTITY t3_12_a IS(CL,CLK0:IN OUTENDENTITYOFt3_12_a SIGNAL Q : STD_LOGIC;CLK0EVENTANDCLK0=1 Q = NOT(Q OR CL);ENDOFt3_12_a SIGNAL Q : STD_LOGIC;CLK0EVENTANDCLK0=1 Q = NOT(Q OR CL);ENDENDOUT1=NOTENDRTL图-3-20(b)RTLVHDLt3_12_b.vhd LIBRARYIEEE;ENTITY t3_12_b IS(A,B,C,D:INEN

16、D ENTITY t3_12_b;OF t3_12_bSIGNAL AB,CD,ABCD : STD_LOGIC;AB=AANDB; CD=C OR D;ABCD=ABXORCASEABIS WHENWHEN-caseWHENENDENDENDRTL图-13-20(c)RTLRTL图-13-20(c)RTLVHDLmux21a.vhd用(WHEN_ELSE)21多路选择器程序(mux21a.vhd)ENTITY mux21a ISPORT(a,b :IN STD_LOGIC; s :IN STD_LOGIC; y:OUTSTD_LOGIC);END ENTITY mux21a; ARCHITE

17、CTUREoneOFmux21aIS WHENs=0ELSEENDARCHITECTURE-23-20(c)RTLVHDLDFF6.vhdD型触发器程序(DFF6.vhd) LIBRARYIEEE;ENTITY DFF6 ISPORT(CLK: IN STD_LOGIC; D: IN STD_LOGIC; Q:OUTSTD_LOGIC);ARCHITECTUREbhvOFDFF6IS IF CLK=1 THENQ=D;ENDENDEND-33-20(c)RTLVHDLt3_12_c.vhdENTITY t3_12_c IS INQ:OUTENDARCHITECTUREoneOFt3_12_cC

18、OMPONENT-21PORT(a,b :IN STD_LOGIC; s :IN STD_LOGIC;ENDARCHITECTUREoneOFt3_12_cCOMPONENT-21PORT(a,b :IN STD_LOGIC; s :IN STD_LOGIC; y:OUTSTD_LOGIC);ENDCOMPONENT-DPORT(CLK: IN STD_LOGIC; D: IN STD_LOGIC; Q:OUTSTD_LOGIC);ENDSIGNALDD-1mux21aPORTENDARCHITECTURERTL图-13-20(d)RTLVHDLDFF_PRE.vhdD触发器程序(DFF_PR

19、E.vhd)ENTITY DFF_PRE_CLR_ENA ISPORT(CLK:INSTD_LOGIC; D : IN STD_LOGIC; Q:OUTENA: IN STD_LOGIC; PRE : IN STD_LOGIC; CLR : INARCHITECTUREbhvOFDFF_PRE_CLR_ENASIGNALIF CLR=1 THEN Q1=0; ELSIFPRE=1THENQ1=1;ELSIFCLKEVENTANDCLK=1ANDENA=1THENEND-IFEN=1THEN-ENDENDENDEND-IFEN=1THEN-ENDENDEND-23-20(d)RTLVHDLt3_

20、12_d.vhdENTITY t3_12_d IS INQ:OUTEND ENTITYARCHITECTUREoneOFt3_12_dISCOMPONENTDFF_PRE_CLR_ENA PORT(CLK : IN STD_LOGIC;D : IN STD_LOGIC; Q:OUTENA: IN STD_LOGIC; PRE : IN STD_LOGIC; CLR: IN END-DSIGNALSS-1SS=SETAND(NOT ENDARCHITECTURERTL图-13-20(e)RTLVHDLDFF_PRE_CLR.vhdD触发器程序(DFF_PRE_CLR.vhd) LIBRARYIE

21、EE;ENTITY DFF_PRE_CLR_ENA ISPORT(CLK:IND : IN STD_LOGIC; Q:OUTSTD_LOGIC;ENA: IN PRE : IN STD_LOGIC; CLR:INSTD_LOGIC);ARCHITECTUREbhvOFDFF_PRE_CLR_ENASIGNALENA: IN PRE : IN STD_LOGIC; CLR:INSTD_LOGIC);ARCHITECTUREbhvOFDFF_PRE_CLR_ENASIGNALIF CLR=1 THEN Q1=0; ELSIFPRE=1THENQ1=1;ELSIFCLKEVENTANDCLK=1AN

22、DENA=1THENEND-IFEN=1THEN-ENDENDEND-23-20(e)RTLVHDLt3_12_d.vhdENTITY t3_12_e IS INQ1,Q:OUTSTD_LOGIC); END ENTITYARCHITECTUREoneOFt3_12_eCOMPONENTDFF_PRE_CLR_ENA PORT(CLK : IN STD_LOGIC;D : IN STD_LOGIC; Q:OUTENA: IN STD_LOGIC; PRE : IN STD_LOGIC; CLR: IN END-DSIGNALD_EN-1D_EN=DANDQ1=(NOT D_EN) OR RST

23、;ENDARCHITECTURERTL图-13-20(f)RTLVHDLRTL图-13-20(f)RTLVHDLmux21a.vhd用WHEN_ELSE实现2选1多路选择器程序(mux21a.vhd) ENTITY mux21a ISPORT(a,b :IN STD_LOGIC; s :IN STD_LOGIC; y:OUTSTD_LOGIC);END ENTITY mux21a; ARCHITECTUREoneOFmux21aIS WHENs=0ELSEENDARCHITECTURE-23-20(f)RTLVHDLDFF_PRE_CLR.vhdD触发器程序(DFF_PRE_CLR.vhd)

24、LIBRARYIEEE;ENTITY DFF_PRE_CLR_ENA ISPORT(CLK:INSTD_LOGIC; D : IN STD_LOGIC; Q:OUTENA: IN STD_LOGIC; PRE : IN STD_LOGIC; CLR : INARCHITECTUREbhvOFDFF_PRE_CLR_ENASIGNAL-IF CLR=1 THEN Q1=0; ELSIFPRE=1THENQ1=1;ELSIFCLKEVENTANDCLK=1ANDENA=1THENEND-IFEN=1THEN-ENDIF; ENDEND-33-20(f)RTLVHDLt3_12_d.vhdENTIT

25、Y t3_12_f ISPORT(RST,D,CLK :IN STD_LOGIC; Q,DOUT:-ENDIF; ENDEND-33-20(f)RTLVHDLt3_12_d.vhdENTITY t3_12_f ISPORT(RST,D,CLK :IN STD_LOGIC; Q,DOUT:OUTSTD_LOGIC);ENDARCHITECTUREoneOFt3_12_fCOMPONENTDFF_PRE_CLR_ENA PORT(CLK : IN STD_LOGIC;D : IN STD_LOGIC; Q:OUTENA: IN STD_LOGIC; PRE : IN STD_LOGIC; CLR:

26、 IN END-DCOMPONENT-DPORT(a,b :IN STD_LOGIC; s :IN STD_LOGIC; y:OUTSTD_LOGIC);ENDSIGNALDD,DDD-1DDD=D XOR DD;DFF_PRE_CLR_ENA PORT MAP(CLK,DD,Q,1,0,0);ENDARCHITECTURE4习题 测试。4-354-36CNT10 的硬件工作情况。SignalTap II加入独立采样时钟?试给出完整的程序和对它的实测结QuartusIIHelpAssignments(1)TimingRequirements&Qptions(2)Compilations (3)

27、ysis&Synthesis Setting 的功能和使用方法，以及其中的 Synthesis Optimization(4)FitterSettingsDesignAssistantSimulator74148Optimization(4)FitterSettingsDesignAssistantSimulator74148（8-3 ）8421BCD 74139（2线-4。74283（4 位二进制全加器）8421BCD BCD 码，CI 为低位的进位信号，CO AS7人表决电路（4位二进制全加器7人表决电路（4位二进制全加器71意为 基 于 原 理 图 输 入 方 式 ， 用D触 发 器按

28、循 环 码 4 474299（8 位通用移位寄存器、74373（8D 锁存器、D 74163（4 位二进制计数器）74138（3 线-8 ）12112路输出的位置。74195（4位通用移位寄存器）74163 （4位二进制计数器5511-解：4-125-5511-解：4-125-LIBRARY IEEE;USE USE ENTITY DOWNTO 0);-P_out:END ENTITY odd_even_p_RXD_5; ARCHITECTUREoneOFodd_even_p_RXD_5ISshift_Q:DOWNTO0);-shift_Qt:STD_LOGIC_VECTOR(2DOWNTOI

29、FCLKEVENTANDCLK=1 IF RST = 1 THENt=4 shift_Q:=S_in&shift_Q(4DOWNTO1);shift_Q:=S_in&shift_Q(4DOWNTO1);-采样移位串行输入 END IF;END END END ENDARCHITECTURE 7490（十进制计数器）872 shift_Q:=S_in&shift_Q(4DOWNTO1);-采样移位串行输入 END IF;END END END ENDARCHITECTURE 7490（十进制计数器）872 84215习题固有延时惯性延时是什么?VHDL用处STD_LOGICLIBRARY IEE

30、E;USE USE ENTITYDVF D: STD_LOGIC_VECTOR(7DOWNTO0);:END ENTITY DVF; ARCHITECTUREoneOFDVFIS SIGNAL FULL : STD_LOGIC;P_REG: VARIABLECNT8 :STD_LOGIC_VECTOR(7 DOWNTOIFCLKEVENT ANDCLK 1THEN IFCNT8= CNT8 := FULL = ELSECNT8 FULL =END END 当1;FULL:=CNT8+ VARIABLECNT8 :STD_LOGIC_VECTOR(7 DOWNTOIFCLKEVENT ANDCL

31、K 1THEN IFCNT8= CNT8 := FULL = ELSECNT8 FULL =END END 当1;FULL:=CNT8+ END S P_REG P_DIV: VARIABLECNT2: IF CNT2 := ANDFULL 1 IF CNT2 = 1 THENFOUT=1; ELSE FOUT =4THENG_4=1;ELSEG_4qqqq0101)cmp_out=151。 cmp_out=050ENDENDENDVHDL01001011001-1：5-11 VHDLUSEENTITYS_generatorINSTD_LOGIC;工作时钟/S_out:OUTSTD_LOGIC

32、);-序列输出位 END S_generator;ARCHITECTUREbehavOFS_generatorSIGNALDSTD_LOGIC_VECTOR(10DOWNTO-11IFCLKEVENTANDCLK=1IFCLR=1THEND=0100101100111D(10DOWNTO1)=D(9DOWNTO0); END IF;ENDENDEND25- 74194(4位双向通用移位寄存器)、74273(8D触发器)、D874194(4位双向通用移位寄存器)、74273(8D触发器)、D88位一组数据全部转换结束后，5-88-解：8CHDLUSE -8PORT(CLK,LOAD:INDIN:

33、INSTD_LOGIC_VECTOR(7DOWNTO0); QB:OUT STD_LOGIC);ENDARCHITECTUREbehavOFSHFLT8IS VARIABLEREG8:STD_LOGIC_VECTOR(7DOWNTO0); IFCLKEVENTANDIF LOAD=1THEN REG8:=DIN;ELSE REG8(7 DOWNTO 1):=REG8(6 DOWNTO 0); -ENDENDENDENDbehav SVARIABLEREG8:STD_LOGIC_VECTOR(7DOWNTO0); IFCLKEVENTANDIF LOAD=1THEN REG8:=DIN;ELSE

34、 REG8(7 DOWNTO 1):=REG8(6 DOWNTO 0); -ENDENDENDENDbehav S5-15IFLIBRARY USE ENTITY e2 END ARCHITECTUREmultiple_driversOF e2 IFenable=00THENoutput=input3; ELSE outputZ);END END IFenable=01THENoutput=input2; ELSE outputZ);END END IFenable=10THENoutput=input1; ELSE outputZ);END END IFenable=11THENoutput

35、=input0; ELSE outputZ);END END END ARCHITECTURE 题6-1 MegawizardLIBRARY USE END END ARCHITECTURE 题6-1 MegawizardLIBRARY USE COMPONENT GENERIC(lpm_direction:STRING; lpm_port_updown(7 DOWNTO lpm_type:STRING; :PORT(clock:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR END COMPONENT;ponent:GENERICMAP(lpm_direction=UP,

36、lpm_port_updown=PORT_UNUSED, lpm_type = LPM_COUNTER,lpm_width = 8)PORT MAP (clock= clock,q = （SINGTcounter.vh）LIBRARY USEieee.std_logic_1164.all; LIBRARY lpm;USE ENTITY SINGT_counter PORT(clock:INSTD_LOGIC;q: OUTSTD_LOGIC_VECTOR (7DOWNTO END ARCHITECTURESYN OFsingt_counter SIGNAL :STD_LOGIC_VECTOR (

37、7DOWNTO COMPONENTlpm_counter : : lpm_port_updown : : PORT(clock:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(7DOWNTO0); END COMPONENT;qUP,lpm_port_updown=PORT_UNUSED, lpm_type = LPM_COUNTER,lpm_width = 8)PORT MAP (clock =clock,q = END 6-2 LPM_ROM、LPM_RAM、LPM_FIFOFPGAEAB、ESB、M4K答：ACEXlKGENERICMAP(lpm_direction=

38、UP,lpm_port_updown=PORT_UNUSED, lpm_type = LPM_COUNTER,lpm_width = 8)PORT MAP (clock =clock,q = END 6-2 LPM_ROM、LPM_RAM、LPM_FIFOFPGAEAB、ESB、M4K答：ACEXlKQuartusIIHelp(Contents)LPMaltcam、altsyncram、 lpm_fifo、lpm_shiftreg7 题7-1 根据图 7-30(a)所示的状态图，分别按照图 7-30(b)和图 7-30(c)7-307-1-LIBRARY USE ENTITY e_8_16_a

39、_bina:IN CLK,RESET: STD_LOGIC_VECTOR(2DOWNTO0); STD_LOGIC_VECTOR(3DOWNTOEND ENTITY ARCHITECTUREbehavOF e_8_16_a_b TYPEST_TYPEIS(S0,S1,S2,S3); SIGNAL C_ST: ST_TYPE;FSM: IF RESET=1 THENELSIFCLKEVENTANDCLK=1 CASE C_ST ISIF ina=101 ELSIFina=111 END IF;THEN THEN IFina=110THEN ENDIF;ELSIFTYPEST_TYPEIS(S0,S1,S2,S3); SIGNAL C_ST: ST_TYPE;FSM: IF RESET=1 THENELSIFCLKEVE