vga显示颜色动画练习参考代码

1、明德扬科技教育VGA 显示颜色动画练习参考代码官网：淘宝：群目录vga_driver 模块3vga_exec4 模块8明德扬科技公司主要是以 FPGA 为，专业从事 FPGA 配套开发板、FPGA加入明德扬 FPGA培训班或其他培训、研发 FPGA 技术开发、承接 FPGA 项目开发。欢迎和 ASIC97925396。明德扬以 PDF 格式提供源代码，是为了鼓励大家多思考，不要拿来就用，否则是学不好 FPGA 的。本代码对应的设计思路，请参考明德扬课程。vga_driver 模块module vga_driver(clk, rst_n, hys, vys,lcd_rgb); PICTURE_W

2、ROW_Wparameterparameter=8 ;10;parameterTIME_1S= 25000000;parameter parameter parameter parameter parameter parameter parameter parameterparameterWHITE RED GREEN BLUE YELLOW PURPLE CYAN PINKBLACK= 8b111_111_11;= 8b111_000_00;= 8b000_111_00;= 8b000_000_11;= 8b111_111_00;= 8b011_000_10;= 8b011_111_11;=

3、 8b111_011_01;= 8b000_000_00;inputinputclkrst_n;outputoutputhysvys;output PICTURE_W-1:0 lcd_rgb;regPICTURE_W-1:0 lcd_rgb;reg reg reg regregROW_W-1:0ROW_W-1:0t;t;hys; vys;valid_area ;reg24:0reg 3:0reg7:0reg7:0reg7:0reg7:0reg7:0cnt_1s; cnt_15s; lcd_data_1st; lcd_data_2nd; lcd_data_3rd; lcd_data_4th;lc

4、d_data_5th;always(edge clk or negedge rst_n)beginif(rst_n=1b0)begin cnt_1s = 0;endelse if(cnt_1s=TIME_1S-1) begin cnt_1s = 0;endelse begincnt_1s = cnt_1s + 1;endendalways(edge clk or negedge rst_n)beginif(rst_n=1b0)begin cnt_15s = 0;endelse if(cnt_1s=TIME_1S-1) begin if(cnt_15s=14)cnt_15s = 0;elsecn

5、t_15s = cnt_15s + 1;endendalways(edge clk or negedge rst_n)beginif(!rst_n)begint = 10d0;endelse if(t = 10d799)begint = 10d0;endelse begint =endt+1b1;endalways(edge clk or negedge rst_n)beginif(!rst_n) begint = 10d0;endelse if(t = 10d799)beginif(t=524)t = 0;elset =t+1;endendalways(edge clk or negedge

6、 rst_n)beginif(!rst_n)beginhys = 0;endelse if(t=10d95)beginhys = 1b1;endelse if(t=10d799)beginhys = 1b0;endendalways(edge clk or negedge rst_n)beginif(!rst_n)beginvys = 1b0;endelse if(t10d2)beginvys = 1b0;endelse beginvys =141 &endt =32 &t =32 &t=141 &t=32 &t=464 &t=786)beginlcd_data_3rd =274 &t=141

7、 &t=463)beginlcd_data_3rd =274 &t=464 &t=786)beginlcd_data_3rd =(32 + 0) & 215)beginlcd_data_4th = RED;endt=(141+0) &t=(32 + 0) &t=(141+215) &t=(32 + 0) &t=(141+430) &t=(32 + 161) &t=(141+0) &t=(32 + 161) &t=(141+215) &t=(32 + 161) &t=(141+430) &t=(32 + 322) &t=(141+0) &t=(32 + 322) &t=(141+215) &t=

8、 (141+ 0) &t = (141+626) & t = ( 32+ 0) & t = ( 32+464) &t (141+ 20) |t (141+646) | t ( 32+ 20) |t = (141+248) &t (141+398) &t = ( 32+192) &lcd_data_5th = RED;endelse beginlcd_data_5th = WHITE;endendalways(edge clk or negedge rst_n)beginif(rst_n=1b0)begin lcd_rgb = 8h0;endelse if(valid_area)begin if

9、(cnt_15s 3)lcd_rgb = lcd_data_1st; else if(cnt_15s 6)lcd_rgb = lcd_data_2nd; else if(cnt_15s 9)lcd_rgb = lcd_data_3rd; else if(cnt_15s 12)lcd_rgb = lcd_data_4th;elselcd_rgb = lcd_data_5th;endelse beginlcd_rgb = 0;endendendmodulevga_exec4 模块module vga_exec4(clk rst_n lcd_hslcd_vs,lcd_rgb);parameterPI

10、CTURE_W = 8;input input output outputoutputclk rst_n lcd_hslcd_vs;PICTURE_W-1:0 lcd_rgb;/*模块 1 pll 模块*明德扬科教 注释开始*输出接口定义明德扬科教 注释结束*/wireclk_0;/*模块 6 vga 输出接口定义*明德扬科教 注释开始*明德扬科教 注释结束*/= 10 ;parameter wirewireROW_Wlcd_hs;lcd_vs;wire PICTURE_W-1:0 lcd_rgb;/*模块 1 pll 模块*明德扬科教 注释开始*例化明德扬科教 注释结束*/vga_pllmodule_1(.inclk