基于单片机数字时钟设计开题报告书

1、.1毕业设计论文材料之二2本科毕业设计(论文)开题报告题目： 基于单片机数字时钟设计The Design of Digital Clock Based OnA Singlechip课 题 类 型：设计实验研究 论文学 生 姓 名： 专 业 班 级： 学 号： 教 学 单 位： 指 导 教 师： 开 题 时 间： 2021年月 日2021年月日毕业设计论文容及研究意义(价值)1.设计论文容本论文主要研究基于单片机的数字时钟设计。当程序执行后，显示计时时间。设置4个操作键：K1：设置键；K2：上调键；K3：下调键；K4：确定键。，由左向右分别为：时、分、秒。完成显示由秒01一直加1至59，再恢复为

2、00；分加1，由00至01，一直加1至59，再恢复00；时加1，时由00加至23之后秒、分、时全部清清零。该钟使用T0作250us的定时中断。走时调整：走时过程中直接调整且不影响走时准确性，按下时间选择键对“时、分、秒显示进展调整，每按一下时间加，即加1，时间减，即减1。附加功能：星期，年、月、日，温度检测。本设计的主要容：1、了解单片机技术的背景及开展现状，熟悉数字时钟各模块的工作原理；2、选择适当的芯片和元器件，确定系统电路，绘制电路原理图，尤其是各接口电路；3、熟悉单片机使用方法和C语言的编程规则，编写出相应模块的应用程序；4、分别在各自的模块中调试出对应的功能，在Proteus软件上进

3、展仿真。2.研究意义及价值20世纪末，电子技术获得了飞速的开展，在其推动下，现代电子产品几乎渗透了社会的各个领域，有力地推动了社会生产力的开展和社会信息化程度的提高，同时也使现代电子产品性能进一步提高，产品更新换代的节奏也越来越快。时间对人们来说总是则珍贵，工作的忙碌性和繁杂性容易使人忘记当前的时间。忘记了要做的事情，当事情不是很重要的时候，这种遗忘无伤大雅。但是，一旦重要事情，一时的耽误可能酿成大祸。目前，单片机正朝着高性能和多品种方向开展趋势将是进一步向着CMOS化、低功耗、小体积、大容量、高性能、低价格和外围电路装化等几个方面开展。下面是单片机的主要开展趋势。单片机应用的重要意义还在于，

4、它从根本上改变了传统的控制系统设计思想和设计方法。从前必须由模拟电路或数字电路实现的大局部功能，现在已能用单片机通过软件方法来实现了。这种软件代替硬件的控制技术也称为微控制技术，是传统控制技术的一次革命。单片机模块中最常见的是数字钟，数字钟是一种用数字电路技术实现时、分、秒计时的装置，与机械式时钟相比具有更高的准确性和直观性，且无机械装置，具有更更长的使用寿命，因此得到了广泛的使用数字钟是采用数字电路实现对.时,分,秒.数字显示的计时装置,广泛用于个人家庭,车站,码头办公室等公共场所,成为人们日常生活中不可少的必需品,由于数字集成电路的开展和石英晶体振荡器的广泛应用,使得数字钟的精度,远远超过

5、老式钟表, 钟表的数字化给人们生产生活带来了极大的方便，而且大扩展了钟表原先的报时功能。诸如定时自动报警、按时自动打铃、时间程序自动控制、定时播送、自动起闭路灯、定时开关烘箱、通断动力设备甚至各种定时电气的自动启用等，所有这些，都是以钟表数字化为根底的。因此，研究数字钟及扩大其应用，有着非常现实的意义。毕业设计论文研究现状和开展趋势文献综述目前单片机渗透到我们生活的各个领域，几乎很难找到哪个领域没有单片机的踪迹。导弹的导航装置，飞机上各种仪表的控制，计算机的网络通讯与数据传输，工业自动化过程的实时控制和数据处理，广泛使用的各种智能IC卡，录像机、摄像机，以及程控玩具、电子宠物等等，这些都离不开

6、单片机。更不用说自动控制领域的机器人、智能仪表、医疗器械了。因此，单片机的学习、开发与应用将造就一批计算机应用与智能化控制的科学家、工程师。单片机在多功能数字钟中的应用已是非常普遍的，人们对数字钟的功能及工作顺序都非常熟悉。但是却很少知道它的部构造以及工作原理。由单片机作为数字钟的核心控制器，可以通过它的时钟信号进展时实现计时功能，将其时间数据经单片机输出，利用显示器显示出来。通过键盘可以进展定时、校时功能。输出设备显示器可以用液晶显示技术和数码管显示技术。三、 毕业设计论文研究方案及工作方案含工作重点与难点及拟采用的途径1、研究方案本设计采用型号为AT89C52的单片机。器件采用ATMEL公

7、司的高密度、非易失性存储技术生产，兼容标准MCS-52指令系统，片置通用8位中央处理器和Flash存储单元，采用7段LED 数码管显示时、分、秒，以24小时计时方式，根据数码管动态显示原理来进展显示，用12MHz 的晶振产生振荡脉冲，定时器计数。2、工作重点与难点本次设计的单片机数字时钟系统中，其难点主要来源包括晶体频率误差，定时器溢出误差，延迟误差的降低。晶体频率产生震荡，容易产生走时误差；定时器溢出的时间误差，本应这一秒溢出，但却在下一秒溢出，造成走时误差；延迟时间过长或过短，都会造成与基准时间产生偏差，造成走时误差。因此，在选用芯片、器件、硬件时注意它们的性能优劣;烧入程序后，LED液晶

8、显示屏不显示或者亮度不好。不显示时首先使用万用表对电路进展测试,观察是否存在漏焊,虚焊,或者元件损坏的现象。假设无此问题查看烧写的程序是否正确无误，对程序进展认真修改。当显示亮度不好时一遍旋转10K欧的滑动变阻器，一遍观看LED显示屏，直到看到适宜的亮度为止。经过屡次的反复调试试与分析,可以对电路的原理及功能更加熟悉,同时提高了设计能力与及对电路的分析能力。3、工作方案起止日期日/月周次 容 进 程备 注承受设计的课题，查找相关参考文献和资料熟悉设计的课题，查阅、整理参考文献和资料。学习相关参考文献和资料。2.253.101-2撰写开题报告,开题辩论，对设计课题的方案作初步论证3.114.73

9、-6方案论证，软件编程及仿真4.85.57-10熟悉毕业论文格式，撰写论文初稿5.65.1911-12完成论文初稿，提交论文初稿5.206.1613-16修改毕业论文，总体完善6.176.2317完成论文终稿，提交论文终稿，参加论文辩论四、主要参考文献不少于10篇，期刊类文献不少于7篇，应有一定数量的外文文献，至少附一篇引用的外文文献3个页面以上及其译文1王法能. 单片机原理及应用M. 科学,20042 宁. 单片机技术应用根底M. :信息职业技术学院, 20053 勇. 数字电路 M. 电子工业, 20054 子文. 单片机原理及应用M. 电子科技大学2006 5岂兴明，唐杰等 .51单片机

10、编程根底与开发实例详解M. 人民邮电,2021 6 毅刚. 新编MCS-51单片机应用设计M. : 工业大学, 2003 7 朱定华，等. 单片微机原理与应用M. : 清华大学, :交通大学出版,20038 Ling Zhenbao, Wang Jun, Qiu Chunling. Study of Measurement for the Anomalous Solid MatterC. The Si*th International Conference on Measurement and Control of Granular Materials.2003:181-184.9 8-bit

11、 Microcontroller With 8K Bytes in-system programble Flash AT89S52. ATMEL, 2001.10 8-bit Microcontroller With 20K Bytes Flash AT89C55WD.ATMEL,2000.11 期刊:ISSN 1009-623* . 单片机与嵌入式系统应用 : 航空航天大学,2001附英文文献及译文8-bit Microcontroller With 8K ByteFlash AT89C52Featurespatible with MCS-51 Products8K Bytes of In-

12、System Reprogrammable Flash MemoryEndurance: 1,000 Write/Erase CyclesFully Static Operation: 0 Hz to 24 MHzThree-level Program Memory Lock256 * 8-bit Internal RAM32 Programmable I/O LinesThree 16-bit Timer/CountersEight Interrupt SourcesProgrammable Serial ChannelLow-power Idle and Power-down ModesD

13、escriptionThe AT89C52 is a low-power, high-performance CMOS 8-bit microputer with 8K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is patible with the industry-standard 80C51 and 80C52 instruc

14、tion set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By bining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microputer which provides a highly-fle*ible and cost-eff

15、ective solution to many embedded control applications.Pin ConfigurationsBlock DiagramPin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used

16、 as high-impedance inputs. Port 0 can also be configured to be the multiple*ed low-order address/data bus during accesses to e*ternal program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during progra

17、m verification. E*ternal pull-ups are required during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be

18、used as inputs. As inputs, Port 1 pins that are e*ternally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 e*ternal count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2E*), respectivel

19、y, as shown in the following table. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they

20、are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are e*ternally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from e*ternal program memory and during accesses to e*te

21、rnal data memories that use 16-bit addresses (MOV* DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to e*ternal data memories that use 8-bit addresses (MOV* RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the

22、high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull

23、-ups and can be used as inputs. As inputs, Port 3 pins that are e*ternally being pulled low will source current (IIL) because of the pull-ups.Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table. Port 3 also receives some control signals for Fl

24、ash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/ eq * to (PROG) Address Latch Enable is an output pulse for latching the low byte of the address during accesses to e*ternal memory. This pin is also the p

25、rogram pulse input () during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for e*ternal timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to e*ternal data memory. If desired, ALE op

26、eration can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOV* or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in e*ternal e*ecution mode. eq * to (PSEN) Program Store

27、 Enable is the read strobe to e*ternal program memory. When the AT89C52 is e*ecuting code from e*ternal program memory, is activated twice each machine cycle, e*cept that two activations are skipped during each access to e*ternal data memory. eq * to (EA) /VPPE*ternal Access Enable. must be strapped

28、 to GND in order to enable the device to fetch code from e*ternal program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, will be internally latched on reset. EA should be strapped to VCC for internal program e*ecutions. This pin also receives the 12-

29、volt programming enable voltage (VPP ) during Flash programming when 12-volt programming is selected.*TAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.*TAL2Output from the inverting oscillator amplifier.Special Function RegistersA map of the on-chip m

30、emory area called the Special Function Register (SFR) space is shown in the Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indet

31、erminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 RegistersControl and status bits are contained in registers T2CON and

32、T2MOD for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Interrupt RegistersThe individual interrupt enable bits are in the IE register. Two priorities can be set for each of the si* interrupt sources in the

33、IP register.Data MemoryThe AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.When an instruction access

34、es an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For e*ample, the following direct addressing instruction accesses the SFR at l

35、ocation 0A0H .MOV 0A0H, *dataInstructions that use indirect addressing access the upper 128 bytes of RAM. For e*ample, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV R0, *dataNote that stack op

36、erations are e*amples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.Timer 0 and 1Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in the AT89C51.Timer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an e

37、vent counter. The type of operation is selected by bit C/T2 in the SFR T2CON.Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3.Timer 2 consists of two 8-bit registers, TH2 and TL2. In t

38、he Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding e*ternal in

39、put pin, T2. In this function, the e*ternal input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the ne*t cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transi

40、tion was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the ma*imum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machi

41、ne cycle.Capture ModeIn the capture mode, two options are selected by bit E*EN2 in T2CON. If E*EN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON.This bit can then be used to generate an interrupt. If E*EN2 = 1, Timer 2 performs the same operation, but a 1-to-0 t

42、ransition at e*ternal input T2E* also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2E* causes bit E*F2 in T2CON to be set. The E*F2 bit, like TF2 can generate an interrupt. The capture mode is illustrated in Figure 1.Aut

43、o-reload (Up or Down Counter)Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD. Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN

44、is set, Timer 2 can count up or down, depending on the value of the T2E* pin.Figure 2 shows Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit E*EN2 in T2CON. If E*EN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow a

45、lso causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If E*EN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at e*ternal input T2E*. This transitio

46、n also sets the E*F2 bit. Both the TF2 and E*F2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 3. In this mode, the T2E* pin controls the direction of the count. A logic 1 at T2E* makes Timer 2 count up. The timer will overflow

47、 at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2E* makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The unde

48、rflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The E*F2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, E*F2 does not flag an interrupt.文献译文：8位8字节闪存单片机AT89C52主要性能与MCS-51单片机产品兼容8K字节在系统可编程Flash

49、存储器1000次擦写周期全静态操作：0Hz24Hz三级加密程序存储器2568位部存储器32个可编程I/O口线三个16位定时器/计数器八个中断源可编程串行通道低功耗空闲和掉电模式功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K置可编程闪存。产品使用了Atmel公司高密度非易失性存储器技术制造，与工业80C51和80C52产品指令和引脚完全兼容。片上Flash允许程序存储器在系统可编程，亦适于常规编程器。在单芯片上，拥有灵巧的8位CPU和在系统可编程Flash，使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。引脚构造方框图VCC : 电源GND

50、:地P0口：P0口是一个8位漏极开路的双向I/O口。作为输出口，每位能驱动8个TTL逻辑电平。对P0端口写“1时，引脚用作高阻抗输入。当外部程序和数据存储器时，P0口也被作为低8位地址/数据复用。在这种模式下，P0具有部上拉电阻。在flash编程时，P0口也用来接收指令字节；在程序校验时，输出指令字节。程序校验时，需要外部上拉电阻。P1口：P1 口是一个具有部上拉电阻的8位双向I/O 口，P1 输出缓冲器能驱动4个TTL 逻辑电平。对P1端口写“1时，部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于部电阻的原因，将输出电流IIL。此外，P1.0和P1.2分别作

51、定时器/计数器2的外部计数输入P1.0/T2和时器/计数器2的触发输入P1.1/T2E*，具体如下表所示。在flash编程和校验时，P1口接收低8位地址字节。P2 口：P2 口是一个具有部上拉电阻的8 位双向I/O 口，P2输出缓冲器能驱动4个TTL 逻辑电平。对P2端口写“1时，部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于部电阻的原因，将输出电流IIL。在外部程序存储器或用16位地址读取外部数据存储器例如执行MOV* DPTR时，P2口送出高八位地址。在这种应用中，P2口使用很强的部上拉发送1。在使用8位地址如MOV* RI外部数据存储器时，P2口输出P

52、2锁存器的容。在flash编程和校验时，P2口也接收高8位地址字节和一些控制信号。P3 口：P3口是一个具有部上拉电阻的8 位双向I/O 口，p2输出缓冲器能驱动4个TTL 逻辑电平。对P3端口写“1时，部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于部电阻的原因，将输出电流IIL。P3口亦作为AT89S52特殊功能第二功能使用，如下表所示。在flash编程和校验时，P3口也接收一些控制信号。RST: 复位输入。晶振工作时，RST脚持续2个机器周期高电平将使单片机复位。看门狗计时完成后，RST脚输出96个晶振周期的高电平。特殊存放器AU*R(地址8EH)上的D

53、ISRTO位可以使此功能无效。DISRTO默认状态下，复位高电平有效。ALE/ eq * to (PROG) ：地址锁存控制信号ALE是外部程序存储器时，锁存低8位地址的输出脉冲。在flash编程时，此引脚 eq * to (PROG) 也用作编程输入脉冲。在一般情况下，ALE 以晶振六分之一的固定频率输出脉冲，可用来作为外部定时器或时钟使用。然而，特别强调，在每次外部数据存储器时，ALE脉冲将会跳过。如果需要，通过将地址为8EH的SFR的第0位置“1，ALE操作将无效。这一位置“1，ALE 仅在执行MOV* 或MOVC指令时有效。否则，ALE 将被微弱拉高。这个ALE 使能标志位地址为8EH

54、的SFR的第0位的设置对微控制器处于外部执行模式下无效。 eq * to (PSEN) :外部程序存储器选通信号 eq * to (PSEN) 是外部程序存储器选通信号。当AT89S52从外部程序存储器执行外部代码时， eq * to (PSEN) 在每个机器周期被激活两次，而在外部数据存储器时， eq * to (PSEN) 将不被激活。 eq * to (EA) /VPP:外部程序存储器控制信号。为使能从0000H 到FFFFH的外部程序存储器读取指令， eq * to (EA) 必须接GND。为了执行部程序指令， eq * to (EA) 应该接VCC。在flash编程期间， eq *

55、to (EA) 也接收12伏VPP电压。*TAL1:振荡器反相放大器和部时钟发生电路的输入端。*TAL2:振荡器反相放大器的输出端。特殊功能存放器如图1中所示的存储器区域称为特殊功能存放器。应该注意到，并不是所有的地址都会被定义，单片机中那些没有被定义的地址是无效的。读这些地址一般会返回随机数据，写这些地址则会产生一个不确定的影响。用户软件不应将那些没有被列举出来的地址置1。在这种情况下，复位后这些单元数值总是0。定时/计数器2定时/计数器2的控制和状态位位于T2CON和T2MOD。存放器对RCAO2H、RCAP2L是定时器2在16位捕获方式或16位自动重装载方式下的捕获/自动重装载存放器。中断存放器所有单独的中断允许位都存在于中断允许存放器IE中。中断优先级存放器IP可以为六个中断源设置两个中断优先级。数据存储