集成电路EDA设计技术：DE2实验练习解答

1、Introduction这个练习的目的是学习如何连接简单的输入、输出设备到一个FPGA芯片，并且用这些器件实现一个电路。我们将用DE2开发板上的switches SW17-0作为输入，用LED和7-segment displays作为输出。完成DE2 实验练习1（Digital Logic）对与初学者来说是一个比较大的实验。我估计，每天要花几小时才能完成。这个实验包括6个部分，主要是组合逻辑电路和使用assign语句。Part I ：第一次使用assign语句Altera 的DE2开发板有18个拨动开关（toggle switch）和18个红色的LED。Part I非常简单，在实验手册里首先介

2、绍了Verilog的格式，并给出了代码。需要自己做的部分就是把代码粘贴到Quartus II然后运行。当你拨动一个开关（比如Switch 1），对应的LED就会亮（比如LEDR1），这部分在实验手册里解释的很详细。Part 1代码： 1 /* 2 3 (C) yf.x 2010 / 4 5 Filename : part1.v 6 7 Compiler : Quartus II 9.1 Web Edition 8 9 Description : Demo how to use Switch and led 10 11 Release : 03/05/2010 1.0 12 13 */ 14 1

3、5 /Simple module that conects the SW switchs to the LEDR lights 16 17 module part1(SW,LEDR); 18 19 input 17:0 SW; /toggle switches 20 21 output 17:0 LEDR; /red leds 22 23 assign LEDR=SW; 24 25 endmodulePart II：设计一个8位的2选1多路选择器用Verilog设计一个多路选择器有很多种方法。但是在这个实验里，要求只能用门级电路描述。比如：assign m=(s&x)|(s&y);这里x和y是

4、输入，s是选择信号，m是输出。X被定义为SW 0到7，Y被定义为SW 8到15，S被定义为SW17，M被定义为绿色的LEDG 0到7.这部分的完整代码如下。Part II 代码： 1 /* 2 3 (C) yf.x 2010 / 4 5 Filename : part2.v 6 7 Compiler : Quartus II 9.1 Web Edition 8 9 Description : Demo how to use assign statements 10 11 Release : 03/05/2010 1.0 12 13 */ 14 15 /Top level file of par

5、t2 16 17 module part2(LEDR,LEDG,SW); 18 19 input 17:0SW; 20 21 output 17:0LEDR; 22 23 output 7:0LEDG; 24 25 wire s; 26 27 wire 7:0X,Y,M; 28 29 assign S=SW17; 30 31 assign X=SW7:0; 32 33 assign Y=SW15:8; 34 35 assign LEDR=SW; 36 37 assign LEDG=M; 38 39 mux2to1 m7(S,X7,Y7,M7); 40 41 mux2to1 m6(S,X6,Y6

6、,M6); 42 43 mux2to1 m5(S,X5,Y5,M5); 44 45 mux2to1 m4(S,X4,Y4,M4); 46 47 mux2to1 m3(S,X3,Y3,M3); 48 49 mux2to1 m2(S,X2,Y2,M2); 50 51 mux2to1 m1(S,X1,Y1,M1); 52 53 mux2to1 m0(S,X0,Y0,M0); 54 55 endmodule 56 57 /1-bit 2-to1 multiplexer 58 59 module mux2to1(s,x,y,m); 60 61 input s,x,y; 62 63 output m; 6

7、4 65 assign m=(s&x)|(s&y); 66 67 endmodule 68 69 在我的代码里，有一个小技巧。我把RTL代码分成2部分。1个主模块和1个多路选择器模块。通过调用多选器模块，可以很容易的实现设计。（这里因为用到很多引脚，为了方便引脚分配，输入、输出端口名和板上的器件名相同。）Part III：设计一个3位的5选一多路选择器设计一个3位的5选1多路选择器很简单。如图1所示，使用了4个3位的2选1的多路选择器。完整代码如下：图 1 5选1多路选择器Part III 代码： 1 /* 2 3 (C) yf.x 2010 / 4 5 Filename : part3.v

8、6 7 Compiler : Quartus II 9.1 Web Edition 8 9 Description : Demo how to use assign statements 10 11 Release : 03/05/2010 1.0 12 13 */ 14 15 /3BIT 5 to 1 Multiplexer Module 16 17 module mux_3bit_5to1(S,U,V,W,X,Y,M); 18 19 input2:0S,U,V,W,X,Y; 20 21 output2:0M; 22 23 wire2:0m0,m1,m2; 24 25 / Leftmost

9、2 to 1 Multiplexers 26 27 /Top 28 29 assign m00 = (S0&U0)|(S0&V0); 30 31 assign m01 = (S0&U1)|(S0&V1); 32 33 assign m02 = (S0&U2)|(S0&V2); 34 35 /Bottom 36 37 assign m10 = (S0&W0)|(S0&X0); 38 39 assign m11 = (S0&W1)|(S0&X1); 40 41 assign m12 = (S0&W2)|(S0&X2); 42 43 /Middle Multiplexer 44 45 assign

10、m20 = (S1&m00)|(S1&m10); 46 47 assign m21 = (S1&m01)|(S1&m11); 48 49 assign m22 = (S1&m02)|(S1&m12); 50 51 /Last Multiplexer 52 53 assign M0 = (S2&m20)|(S2&Y0); 54 55 assign M1 = (S2&m21)|(S2&Y1); 56 57 assign M2 = (S2&m22)|(S2&Y2); 58 59 endmodule 60 61 part IV：设计一个7segment 显示“HELLO”这部分要求用一个7segmen

11、t显示H、E、L、O。需要注意DE2上的七段码数码管是共阴极，对应的真值表见表 1 7-segment 译码真值表：c2c1c0character7_segment000H1001000001E0110000010L1110001011O0000001100blank1111111101110111表1 7-segment 译码真值表表达式化简，用卡诺图，比如seg6（上表7-segment的最右边的一列），化简过程如下图所示：Part IV：代码 1 /* 2 3 (C) yf.x 2010 / 4 5 Filename : part4.v 6 7 Compiler : Quartus II

12、 9.1 Web Edition 8 9 Description : Demo how to use 7segment display 10 11 Release : 03/12/2010 1.0 12 13 */ 14 15 /use a 7segment display H、E、L、O 16 17 module part4(SW,LEDR,HEX0); 18 19 input 2:0 SW; 20 21 output 2:0 LEDR; 22 23 output 0:6 HEX0; 24 25 assign LEDR=SW; 26 27 /Seven Segment Decoder for

13、 HELO 28 29 assign HEX00 = SW2|SW0; 30 31 assign HEX01=SW2|(SW1&SW0)|(SW1&SW0); 32 33 assign HEX02=SW2|(SW1&SW0)|(SW1&SW0); 34 35 assign HEX03 = SW2|(SW1&SW0); 36 37 assign HEX04 = SW2; 38 39 assign HEX05 = SW2; 40 41 assign HEX06 = SW2|SW1; 42 43 endmodule 44 45 注：因为要求用连续赋值语句和布尔逻辑实现，对于七段码的每一段的表达式都可

14、以根据真值表先化简（当然综合工具会自动化简，但是如果考综合工具化简，每个表达式就会很长）。化简就会用到我们学过的卡诺图图（以前一直觉得卡诺图用不上L）。Part V：用5个7segment循环显示HELLO这部分要求用5个数码管循环显示HELLO,涉及part III和part IV的引用。5个数码管循环显示如图2.图 2 数码管循环显示HELLOPart V 代码： 1 /* 2 3 (C) yf.x 2010 / 4 5 Filename : part5.v 6 7 Compiler : Quartus II 9.1 Web Edition 8 9 Description : Demo h

15、ow to rotating display 10 11 Release : 03/12/2010 1.0 12 13 */ 14 15 /Top level file 16 17 module part5(SW,HEX4,HEX3,HEX2,HEX1,HEX0); 18 19 input 17:0SW; 20 21 output 0:6 HEX4,HEX3,HEX2,HEX1,HEX0; 22 23 wire 2:0 M4,M3,M2,M1,M0; 24 25 mux_3bit_5to1 N4(SW17:15,SW14:12,SW11:9, 26 27 SW8:6,SW5:3,SW2:0,M

16、4); 28 29 mux_3bit_5to1 N3(SW17:15,SW11:9,SW8:6, 30 31 SW5:3,SW2:0,SW14:12,M3); 32 33 mux_3bit_5to1 N2(SW17:15,SW8:6,SW5:3, 34 35 SW2:0,SW14:12,SW11:9,M2); 36 37 mux_3bit_5to1 N1(SW17:15,SW5:3,SW2:0, 38 39 SW14:12,SW11:9,SW8:6,M1); 40 41 mux_3bit_5to1 N0(SW17:15,SW2:0,SW14:12, 42 43 SW11:9,SW8:6,SW5

17、:3,M0); 44 45 char_7seg H4(M4,HEX4); 46 47 char_7seg H3(M3,HEX3); 48 49 char_7seg H2(M2,HEX2); 50 51 char_7seg H1(M1,HEX1); 52 53 char_7seg H0(M0,HEX0); 54 55 endmodule 56 57 /implements a 7_segment decoder for H,E,L,O,and blank 58 59 module char_7seg(c,display); 60 61 input 2:0c; 62 63 output 0:6di

18、splay; 64 65 /Seven Segment Decoder for HELO 66 67 assign display0 = c2|c0; 68 69 assign display1 = c2|(c0&c1)|(c1&c2&c0); 70 71 assign display2 = c2|(c0&c1)|(c0&c1&c2); 72 73 assign display3 = c2|(c1&c0); 74 75 assign display4 = c2; 76 77 assign display5 = c2; 78 79 assign display6 = c2|c1; 80 81 e

19、ndmodule 82 83 /3BIT 5 to 1 Multiplexer Module 84 85 module mux_3bit_5to1(S,U,V,W,X,Y,M); 86 87 input2:0S,U,V,W,X,Y; 88 89 output2:0M; 90 91 wire2:0m0,m1,m2; 92 93 / Leftmost 2 to 1 Multiplexers 94 95 /Top 96 97 assign m00 = (S0&U0)|(S0&V0); 98 99 assign m01 = (S0&U1)|(S0&V1); 100 101 assign m02 = (

20、S0&U2)|(S0&V2); 102 103 /Bottom 104 105 assign m10 = (S0&W0)|(S0&X0); 106 107 assign m11 = (S0&W1)|(S0&X1); 108 109 assign m12 = (S0&W2)|(S0&X2); 110 111 /Middle Multiplexer 112 113 assign m20 = (S1&m00)|(S1&m10); 114 115 assign m21 = (S1&m01)|(S1&m11); 116 117 assign m22 = (S1&m02)|(S1&m12); 118 11

21、9 /Last Multiplexer 120 121 assign M0 = (S2&m20)|(S2&Y0); 122 123 assign M1 = (S2&m21)|(S2&Y1); 124 125 assign M2 = (S2&m22)|(S2&Y2); 126 127 endmodule 128 129 技巧：同样的选择参数被用于不同的多路选择器实例引用，不同的多路选择器连接不同的数码管，每个数码管都可以循环显示不同的字符。前两部分的代码稍稍修改就可直接引用。Part VI：用8个数码管循环显示HELLO要求按照图 3 数码管循环显示，这是整个实验最复杂的部分，需要用到前5部分的

22、信息。因为要用到选择信号的8中状态，需要创建一个8选1的多路选择器。其余就类似第5部分。注意在实例引用8选1多路器时8个输入信号的排列（我的神啊，眼睛差点都看花了J）!图3 数码管循环显示Part VI 代码： 1 /* 2 3 (C) yf.x 2010 / 4 5 Filename : part6.v 6 7 Compiler : Quartus II 9.1 Web Edition 8 9 Description : Demo how to use 8 7seg rotating display 10 11 Release : 03/12/2010 1.0 12 13 */ 14 15

23、/Top level file 16 17 module part6(SW,HEX7,HEX6,HEX5,HEX4,HEX3,HEX2, 18 19 HEX1,HEX0); 20 21 input 17:0SW; 22 23 output 0:6HEX7,HEX6,HEX5,HEX4,HEX3,HEX2, 24 HEX1,HEX0; 25 26 wire 2:0M7,M6,M5,M4,M3,M2,M1,M0; 27 28 mux_3bit_8to1 N7(SW17:15,SW2:0,SW2:0,SW2:0, SW14:12,SW11:9,SW8:6,SW8:6,SW5:3,M7); 29 30

24、 mux_3bit_8to1 N6(SW17:15,SW2:0,SW2:0,SW14:12, SW11:9,SW8:6,SW8:6,SW5:3,SW2:0,M6); 31 32 mux_3bit_8to1 N5(SW17:15,SW2:0,SW14:12, 33 SW11:9,SW8:6,SW8:6,SW5:3,SW2:0,SW2:0,M5); 34 35 mux_3bit_8to1 N4(SW17:15,SW14:12,SW11:9, 36 SW8:6,SW8:6,SW5:3,SW2:0,SW2:0,SW2:0,M4); 37 38 mux_3bit_8to1 N3(SW17:15,SW11

25、:9,SW8:6,SW8:6, SW5:3,SW2:0,SW2:0,SW2:0,SW14:12,M3); 39 40 mux_3bit_8to1 N2(SW17:15,SW8:6,SW8:6,SW5:3, SW2:0,SW2:0,SW2:0,SW14:12,SW11:9,M2); 41 42 mux_3bit_8to1 N1(SW17:15,SW8:6,SW5:3, 43 SW2:0,SW2:0,SW2:0,SW14:12,SW11:9,SW8:6,M1); 44 45 mux_3bit_8to1 N0(SW17:15,SW5:3,SW2:0,SW 2:0, SW2:0,SW14:12,SW1

26、1:9,SW8:6,SW8:6,M0); 46 47 char_7seg H7(M7,HEX7); 48 49 char_7seg H6(M6,HEX6); 50 51 char_7seg H5(M5,HEX5); 52 53 char_7seg H4(M4,HEX4); 54 55 char_7seg H3(M3,HEX3); 56 57 char_7seg H2(M2,HEX2); 58 59 char_7seg H1(M1,HEX1); 60 61 char_7seg H0(M0,HEX0); 62 63 endmodule 64 65 /3bit 8to1 multiplexer 66

27、 67 /use 7 3bit 2-to-1 multiplexer 68 69 module mux_3bit_8to1(S,U,V,W,X,Y,Z,A,B,M); 70 71 input 2:0S,U,V,W,X,Y,Z,A,B; 72 73 output 2:0M; 74 75 wire 2:0n0,n1,n2,n3,n4,n5; 76 77 / 2 to 1 Multiplexers 78 79 /one 80 81 assign n00 = (S0&U0)|(S0&V0); 82 83 assign n01 = (S0&U1)|(S0&V1); 84 85 assign n02 =

28、(S0&U2)|(S0&V2); 86 87 /two 88 89 assign n10 = (S0&W0)|(S0&X0); 90 91 assign n11 = (S0&W1)|(S0&X1); 92 93 assign n12 = (S0&W2)|(S0&X2); 94 95 /three 96 97 assign n20 = (S0&Y0)|(S0&Z0); 98 99 assign n21 = (S0&Y1)|(S0&Z1); 100 101 assign n22 = (S0&Y2)|(S0&Z2); 102 103 /four 104 105 assign n30 = (S0&A0

29、)|(S0&B0); 106 107 assign n31 = (S0&A1)|(S0&B1); 108 109 assign n32 = (S0&A2)|(S0&B2); 110 111 /five 112 113 assign n40 = (S1&n00)|(S1&n10); 114 115 assign n41 = (S1&n01)|(S1&n11); 116 117 assign n42 = (S1&n02)|(S1&n12); 118 119 /six 120 121 assign n50 = (S1&n20)|(S1&n30); 122 123 assign n51 = (S1&n

30、21)|(S1&n31); 124 125 assign n52 = (S1&n22)|(S1&n32); 126 127 /seven 128 129 assign M0 = (S2&n40)|(S2&n50); 130 131 assign M1 = (S2&n41)|(S2&n51); 132 133 assign M2 = (S2&n42)|(S2&n52); 134 135 endmodule 136 137 /implements a 7_segment decoder for H,E,L,O,and blank 138 139 module char_7seg(c,display

31、); 140 141 input 2:0c; 142 143 output 0:6display; 144 145 /Seven Segment Decoder for HELO 146 147 assign display0 = c2|c0; 148 149 assign display1 = c2|(c0&c1)|(c1&c2&c0); 150 151 assign display2 = c2|(c0&c1)|(c0&c1&c2); 152 153 assign display3 = c2|(c1&c0); 154 155 assign display4 = c2; 156 157 ass

32、ign display5 = c2; 158 159 assign display6 = c2|c1; 160 161 endmodule 162 163 注：3位8选1多路器的设计思想如同前面的3位5选1多路器的设计思想一致。在这部分，我预选设置SW的值如表2。SW预设值数码管显示SW14-12000HSW11-9001ESW8-6010LSW5-3011OSW2-0100blankConclusion整体来看，Altera的实验设计很花心思。在实验1，主要要求用基本的布尔逻辑实现。不允许用高级的RTL描述，考查门级电路实现（心中有电路图，描述就不难。J）。完成整个实验非常有趣，积累基本经验

33、，并且回顾和更好的理解底层的数字逻辑设计。Part I 2进制数字的显示在HEX3到HEX0上显示SW15-0的值。SW15-12，SW11-8，SW7-4，SW3-0分别对应于HEX3，HEX2，HEX1，HEX0.在数码管上显示0-9，忽略开关表示的数值1010-1111.本练习的目的是手工推导数码管显示的逻辑，要求只用赋值语句和布尔表达式实现。.part1顶层文件1/part1 display 0-9 on the 7-segment displays2modulepart1(HEX3,HEX2,HEX1,HEX0,SW);3input15:0SW;4output0:6HEX3,HEX2

34、,HEX1,HEX0;56btd H3(SW15:12,HEX3);7btd H2(SW11:8,HEX2);8btd H1(SW7:4,HEX1);9btd H0(SW3:0,HEX0);1011endmodule数码管译码电路：1/binary-to-decimal2modulebtd(s,seg);3input3:0s;4output0:6seg;56assignseg6=s3&s2&s1|s2&s1&s0;7assignseg5=s3&s2&s0|s2&s1|s1&s0;8assignseg4=s0|s2&s1;9assignseg3=s3&s2&s1&s0|10s2&s1&s0|11

35、s2&s1&s0;12assignseg2=s2&s1&s0;13assignseg1=s2&s1&s0|s2&s1&s0;14assignseg0=s2&s1&s0|s3&s2&s1&s0;1516endmodule进制值转换为进制将位二进制输入转换成位十进制数，在和上分别显示和.输出值与输入值的对应关系如表.图给出了电路的部分设计。比较器用来检测电路用来将的输入转换成对应的个位的码电路用来将位二进制的输入转换为对应的码显示.1/part 22modulepart2(V,D1,D0);3input3:0V;4output0:6D1,D0;5wirez;/comparator output6w

36、ire2:0a;/circuit A output7wire3:0m;/multiplexer output89comparator C(V,z);10circuita A(V2:0,a);11mux_4b_2to1 M(V,1b0,a,z,m);12circuitb B(z,D1);13btd D(m,D0);1415endmodule1617/circuit B18modulecircuitb(z,seg);19inputz;20output0:6seg;2122assignseg6=1;23assignseg5=z;24assignseg4=z;25assignseg3=z;26assi

37、gnseg2=0;27assignseg1=0;28assignseg0=z;2930endmodule313233/4-bit 2-to-1 multiplexer34modulemux_4b_2to1(x,y,s,m);35input3:0 x;36input3:0y;37inputs;38output3:0m;3940mux_2to1 u3(x3,y3,s,m3);41mux_2to1 u2(x2,y2,s,m2);42mux_2to1 u1(x1,y1,s,m1);43mux_2to1 u0(x0,y0,s,m0);4445endmodule46/2to1 multiplexer47m

38、odulemux_2to1(a,b,s,m);48inputa,b,s;49outputm;5051assignm=s?b:a;5253endmodule545556/circuit A57modulecircuita(v,a);58input2:0v;59output2:0a;6061assigna2=v2&v1;62assigna1=v2&v1;63assigna0=(v1&v0)|(v2&v0);6465endmodule行波进位加法器.1/4-bit ripple-carry adder circuit2modulepart3(SW,LEDR,LEDG);3input8:0SW;4ou

39、tput8:0LEDR;5output4:0LEDG;6wire3:0a,b;7wirecin;8wire3:0s;9wirecout;10wire3:1c;1112assignLEDR=SW;13assigncin=SW8;14assigna=SW7:4;15assignb=SW3:0;16assignLEDG4=cout;17assignLEDG3:0=s;1819fadder(cin,a0,b0,s0,c1);20fadder(c1,a1,b1,s1,c2);21fadder(c2,a2,b2,s2,c3);22fadder(c3,a3,b3,s3,cout);2324endmodule

40、2526/full adder27modulefadder(ci,a,b,s,co);28inputci,a,b;29outputs,co;3031assigns=ciab,32co=(ab)?ci:b;3334endmodule位加法器注意处理和的最大值+。.1/part IV:BCD adder23/circuit A4modulecircuit_A(s,ao);5input3:0s;6output3:0ao;78assignao3=s3&s2&s1,9ao2=(s3&s2&s1)|(s3&s2&s1),10ao1=(s3&s2&s1)|(s3&s2&s1),11ao0=(s3&s2&s0

41、)|(s3&s2&s0)|12(s2&s1&s0);1314endmodule1516/4-bit 2-to-1 multiplexer17modulemux2to1_4b(x,y,s,m);18input3:0 x,y;19inputs;20output3:0m;2122mux_2to1 u3(x3,y3,s,m3);23mux_2to1 u2(x2,y2,s,m2);24mux_2to1 u1(x1,y1,s,m1);25mux_2to1 u0(x0,y0,s,m0);2627endmodule28/2to1 multiplexer29modulemux_2to1(a,b,s,m);30i

42、nputa,b,s;31outputm;3233assignm=s?b:a;3435endmodule3637/circuit B38modulecircuit_B(z,seg);39inputz;40output0:6seg;4142assignseg6=1;43assignseg5=z;44assignseg4=z;45assignseg3=z;46assignseg2=0;47assignseg1=0;48assignseg0=z;4950endmodule5152/7-segment decoder53modulebtd(s,seg);54input3:0s;55output0:6se

43、g;5657assignseg6=s3&s2&s1|s2&s1&s0;58assignseg5=s3&s2&s0|s2&s1|s1&s0;59assignseg4=s0|s2&s1;60assignseg3=s3&s2&s1&s0|61s2&s1&s0|62s2&s1&s0;63assignseg2=s2&s1&s0;64assignseg1=s2&s1&s0|s2&s1&s0;65assignseg0=s2&s1&s0|s3&s2&s1&s0;6667endmodule6869/4-bit full adder70modulefa_4b(a,b,s,cin,cout);71input3:0a

44、,b;72inputcin;73output3:0s;74outputcout;7576wire3:1c;7778fadder fao(cin,a0,b0,s0,c1);79fadder fa1(c1,a1,b1,s1,c2);80fadder fa2(c2,a2,b2,s2,c3);81fadder fa3(c3,a3,b3,s3,cout);8283endmodule8485/full adder86modulefadder(ci,a,b,s,co);87inputci,a,b;88outputs,co;8990assigns=ciab,91co=(ab)?ci:b;9293endmodu

45、le9495/circuit comparator96modulecomparator(v,z);97input3:0v;98outputz;99100assignz=(v3&v2)|(v3&v1);101102endmodule103104/part 4 top file105modulepart4(SW,LEDR,LEDG,LEDG8,HEX6,HEX4,HEX1,HEX0);106input8:0SW;/Cin,A,B107output8:0LEDR;108output4:0LEDG;109output0:6HEX6,HEX4,HEX1,HEX0;110outputLEDG8;11111

46、2wire3:0sum;/sum113wireco;/cout114wire3:0ao;/circuit_A output115wire3:0m;/mux2to1_4b output116wirez;/comparator output117wirebi;/circuit_B input118wireva,vb;/A,B comparator output119assignLEDR=SW,120LEDG4=co,121LEDG3:0=sum,122LEDG8=va|vb;123assignbi=co|z;124125fa_4b u0(SW7:4,SW3:0,sum,SW8,co);126cir

47、cuit_A u1(sum,ao);127comparator u7(sum,z);128mux2to1_4b u2(sum,ao,bi,m);129btd u3(m,HEX0);130circuit_B u4(bi,HEX1);131btd u5(SW7:4,HEX6);132btd u6(SW3:0,HEX4);133comparator u8(SW7:4,va),134u9(SW3:0,vb);135136137138endmodule139位加法器.1/*.The ADDER CIRUIT.*/2/A Full Adder Circuit3modulefulladder(C,A,B,S

48、,O);4inputC,A,B;5outputS,O;67/C = CarryIn, A & B = Inputs, S = Sum, O = Carryout8assignS=C(AB);9assignO=(AB)&B)|(AB)&C);10endmodule1112/4 Bit, Full Adder Circuit13modulefulladder_4bit(C,A,B,S,O);14inputC;15input3:0A,B;16outputO;17output3:0S;18wire3:0cwire;1920/C=CarryIn, A&B = Inputs, S = Sumb, O =

49、CarryOut, CWIRE= Carry wire between adders21fulladder N0(C,A0,B0,S0,cwire0);22fulladder N1(cwire0,A1,B1,S1,cwire1);23fulladder N2(cwire1,A2,B2,S2,cwire2);24fulladder N3(cwire2,A3,B3,S3,cwire3);2526/BCD Carry27assignO=cwire3|(S3&S2)|(S3&S1);28endmodule2930/BCD Adder: Sum Finder31modulebcdAdder(C,A,B,

50、S,O);32inputC;33input3:0A,B;34output3:0S;35outputO;36wire3:0cwire;37wire3:0preSum;3839fulladder_4bit MidAd1(C,A,B,preSum,O);4041assigncwire0=0;42assigncwire1=O;43assigncwire2=O;44assigncwire3=0;454647fulladder_4bit MidAd2(0,cwire,preSum,S);4849endmodule5051/top_level file52modulepart5(SW,HEX7,HEX6,H

51、EX5,HEX4,HEX2,HEX1,53HEX0);54input16:0SW;55output0:6HEX7,HEX6,HEX5,HEX4,HEX2,HEX1,56HEX0;5758wire3:0s0,s1;59wireco0,co1;6061btd ua1(SW15:12,HEX7);62btd ua0(SW11:8,HEX6);63btd ub1(SW7:4,HEX5);64btd ub0(SW3:0,HEX4);6566bcdAdder u0(SW16,SW11:8,SW3:0,s0,co0);67bcdAdder u1(co0,SW15:12,SW7:4,s1,co1);68cir

52、cuit_B us2(co1,HEX2);69btd us1(s1,HEX1);70btd us0(s0,HEX0);7172endmodule设计思想参考 University of Sulaimani College of Engineering Electrical Engineering Department -Advanced Electronic Lab-fourth Year 2010-2011, prepared by:Mr. Arazs.Ameen.代码 1 module part5(SW,HEX7,HEX6,HEX5,HEX4,HEX2,HEX1,HEX0); 2 inpu

53、t 15:0 SW; 3 output 0:6 HEX7,HEX6,HEX5,HEX4,HEX2,HEX1,HEX0; 4 5 wire 3:0 a1,a0,b1,b0; 6 wire k0,s2; 7 wire 3:0 s1,s0; 8 9 assign a1=SW15:12;10 assign a0=SW11:8;11 assign b1=SW7:4;12 assign b0=SW3:0;13 14 bcd_adder u0(a0,b0,1b0,k0,s0);15 bcd_adder u1(a1,b1,k0,s2,s1);16 17 circuit_B u3(s2,HEX2);18 btd

54、 u4(s1,HEX1);19 btd u5(s0,HEX0);20 btd u6(a1,HEX7);21 btd u7(a0,HEX6);22 btd u8(b1,HEX5);23 btd u9(b0,HEX4);24 25 endmodule module bcd_adder(a,b,cin,k,s); input 3:0 a,b; input cin; output 3:0 s; /bcd_adder sum output k; /bcd_adder cout wire 3:0 sum; wire co; wire 3:0 ao; wire 3:0 m; wire z; wire bi;

55、 assign bi=co|z; fa_4b u0(a,b,sum,cin,co); circuit_A u1(sum,ao); comparator u7(sum,z); mux2to1_4b u2(sum,ao,bi,m); assign k=bi; assign s=m; endmodule ok,至此，解法更完善。另种实现位加法器的方法用结构实现，抽象描述，让编译器去实现具体电路。.1/1-digit bcd_adder2modulebcdadder(Ci,A,B,S,Co);3inputCi;4input3:0A,B;5outputreg3:0S;6outputregCo;78reg

56、3:0z;9reg4:0t;1011always(Ci,A,B)12begin13t=A+B+Ci;14if(t9)15begin16z=4d10;17Co=1b1;18end19else20begin21z=0;22Co=0;23end24S=t-z;25end26endmodule2728/top_level file29modulebcdadder_2(SW,HEX7,HEX6,HEX5,HEX4,HEX2,HEX1,30HEX0);31input16:0SW;32output0:6HEX7,HEX6,HEX5,HEX4,HEX2,HEX1,33HEX0;3435wire3:0s0,s1

57、;36wireco0,co1;3738btd ua1(SW15:12,HEX7);39btd ua0(SW11:8,HEX6);40btd ub1(SW7:4,HEX5);41btd ub0(SW3:0,HEX4);4243bcdadder u0(SW16,SW11:8,SW3:0,s0,co0);44bcdadder u1(co0,SW15:12,SW7:4,s1,co1);45circuit_B us2(co1,HEX2);46btd us1(s1,HEX1);47btd us0(s0,HEX0);4849endmodule解法2：完全照搬伪码 1 /2-digit bcd_adder 2

58、 module part6(SW,HEX7,HEX6,HEX5,HEX4,HEX2,HEX1,HEX0); 3 input 15:0 SW; 4 output 0:6 HEX7,HEX6,HEX5,HEX4,HEX2,HEX1,HEX0; 5 6 wire 3:0 A1,A0,B1,B0; 7 wire 4:0 T1,T0; 8 wire 3:0 S1,S0; 9 wire S2;10 reg 3:0 Z1,Z0;11 reg c1,c2;12 13 assign T0=A0+B0;14 assign T1=A1+B1+c1;15 assign S0=T0-Z0;16 assign S1=T1

59、-Z1;17 assign S2=c2;18 19 always (T1,T0)20 begin21 if(T09)22 begin23 Z0=4d10;24 c1=1b1;25 end26 else27 begin28 Z0=4d0;29 c1=1b0;30 end31 if(T19)32 begin33 Z1=4d10;34 c2=1b1;35 end36 else37 begin38 Z1=4d0;39 c2=1b0;40 end41 end42 43 assign A1=SW15:12;44 assign A0=SW11:8;45 assign B1=SW7:4;46 assign B

60、0=SW3:0;47 48 circuit_B u3(S2,HEX2);49 btd u4(S1,HEX1);50 btd u5(S0,HEX0);51 btd u6(A1,HEX7);52 btd u7(A0,HEX6);53 btd u8(B1,HEX5);54 btd u9(B0,HEX4);55 56 endmodule 位二进制数转换为位十进制数的电路方法：用两个寄存器，一个bit，一个bit，分别存bin码和有待实现的bcd码。接下来，逐位将BIN的最高位移入BCD的最低位。同时，将BCD的16位寄存器按每四位划成一块，我们称之为个十百千好了。但记住，个，十，百，千都有4个bit位