在系统可编程技术：第14讲 VHDL语言语言时序逻辑电路设计

1、在系统可编程技术第14讲 VHDL语言语言时序逻辑电路设计时钟的描述方法上升沿：CPEVENT AND CP=1下升沿：CPEVENT AND CP=0CP=0CP=0CP=1CP=1CPEVENTCPEVENTCPEVENT上升沿D触发器描述方法一：使用信号属性函数LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS(CP)BEGINIF (CPEVEN

2、T AND CP=1) THENQ=D;END PROCESS;END test;方法二：使用WAIT 语句LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESSBEGINWAIT UNTIL CP=1;Q=D;END PROCESS;END test;上升沿D触发器描述方法三：使用上升沿检测函数LIBRARY IEEE;USE IEEE.STD_LOGIC

3、_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS(cp)BEGINIF (rising_edge(cp) THENQ=D;END IF;END PROCESS;END test;上升沿D触发器描述方法四：使用进程的启动特性LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);E

4、ND D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS（CP）BEGINIF CP=1 THENQ=D;END IF;END PROCESS;END test;上升沿D触发器描述上升沿D触发器描述下降沿D触发器描述方法一：使用信号属性函数LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS(CP)BEGINIF

5、 (CPEVENT AND CP=0) THENQ=D;END PROCESS;END test;方法二：使用WAIT 语句LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESSBEGINWAIT UNTIL CP=0;Q=D;END PROCESS;END test;下降沿D触发器描述方法三：使用下降沿检测函数LIBRARY IEEE;USE IEEE.S

6、TD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS(cp)BEGINIF (falling_edge(cp) THENQ=D;END IF;END PROCESS;END test;下降沿D触发器描述方法四：使用进程的启动特性LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD

7、_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS（CP）BEGINIF CP=0 THENQ=D;END IF;END PROCESS;END test;下降沿D触发器描述下降沿D触发器描述髙电平D触发器描述方法：使用进程的启动特性LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS（C

8、P，D）BEGINIF CP=1 THENQ=D;END IF;END PROCESS;END test;髙电平D触发器描述低电平D触发器描述方法：使用进程的启动特性LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(D,CP:IN STD_LOGIC;Q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS（CP，D）BEGINIF CP=0 THENQ=D;END IF;END PROCESS;END test;低电平D触发器描述LIBRAR

9、Y IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY D_reg ISPORT(d,clk,clr:IN STD_LOGIC;q:OUT STD_LOGIC);END D_reg;ARCHITECTURE test OF D_reg ISBEGINPROCESS (clk, clr) BEGIN IF clr = 1 THEN q = 0; ELSIF clkEVENT AND clk = 1 THEN q = d; END IF;END PROCESS;END test;异步复位D触发器异步复位D触发器ARCHITECTURE test OF D_reg ISB

10、EGINPROCESS (clk) BEGIN IF clkEVENT AND clk = 1 THEN IF clr = 1 THEN q = 0; ELSE q = d; END IF; END IF;END PROCESS;END test;同步复位D触发器同步复位D触发器例：设计一异步清零、同步置数的同步8421BCD码计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNT10 IS PORT(CLK,R,S:IN STD_LOGIC;DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0);CO:OUT STD_LOGIC;Q:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);END COUNT10;时序电路设计举例ARCHITECTURE test OF COUNT10 ISBEGINCO=1 WHEN (Q=1001) ELSE 0;PROCESS(CLK