超大规模集成电路第八次作业

1、精选优质文档-倾情为你奉上精选优质文档-倾情为你奉上专心-专注-专业专心-专注-专业精选优质文档-倾情为你奉上专心-专注-专业Assignment 8Access relevant reference books or technical data books and give accurate definitions for the following timing parameters: design entity,signal driver,transaction,event,time queue,delta delay,simulation time,simulation cycle,

2、inertial time, transport time.design entity: In VHDL a given logic circuit represented as a design entity. A design entity, in return , consists of two different types of description: the interface description and one or more architectural bodies. The interface description declares the entity and de

3、scribes its inputs and outputs.signal driver: If a process contains one or more signal assignment statement that schedule future values for some signal X, the VHDL simulator creates a single value holder called a signal driver.transaction:A pair consisting of a value and time. The value part represe

4、nts a future value of the driver; the time part represents the time at which the value part becomes the current value of driver.event: Its a kind of signal property and presents signal jump. Such as if(clkevent and clk=1).time queue: Its used to keep some signal transactions in the simulator. Time q

5、ueue entries are represented as a two-tuple of the form(SN,V), where SN is a signal name and V is the value the signal is scheduled to assume at the scheduled time. Each time queue entry is called a signal transaction.delta delay: A period of time greater than 0, but less than any standard time unit

6、 no number of delta delay added together can cause simulation time to advance.simulation time: The elapsed time in standard time units during simulation.simulation cycle: Every time simulation time advances, a simulation cycle occurs, which we now define more formally. The execution of a model consi

7、sts of an initialization phase followed by the repetitive execution of processes in the process network. Each repetition is said to be a simulation cycle.inertial time: Example: Z = I after 10ns; The signal propagation will take place if and only if input I persists at a given level for 10ns-the amo

8、unt of time specified in the after clause.transport time: Z = transport I after 10ns; All changes on I will propagate to Z, regardless of how long the value of I stays at the new level.Construct VHDL models for 74-139 dual 2-to-4-line decoders using three description types, i.e., behavioral, dataflo

9、w and structural descriptions. Synthesize and simulate these models respectively in the environment of Xilinx ISE with the ModelSim simulator integrated. When simulating these models, test vector(s) are required to stimulate the units under test (UUT). Reasonable test vectors are designed and create

10、d by your own as sources added to your VHDL project. Logic schematic of 74-139:Function table of one decoder of 74-139:INPUTSOUTPUTSENABLESELECTBAY0Y1Y2Y3HXXHHHHLLLLHHHLLHHLHHLHLHHLHLHHHHHL、行为描述代码如下：- Company: - Engineer: - Create Date: 21:14:09 12/02/2016 - Design Name: - Module Name: deceoder_beh

11、- Behavioral - Project Name: - Target Devices: - Tool versions: - Description: - Dependencies: - Revision: - Revision 0.01 - File Created- Additional Comments: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library decl

12、aration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity deceoder_beh isPort ( G1,G2 : in std_logic; A : in std_logic_vector(1 downto 0); B : in std_logic_vector(1 downto 0); Y1 : out std_logic_vector(3 downto 0); Y2 : out std_logic_vector(3 dow

13、nto 0);end deceoder_beh;architecture Behavioral of deceoder_beh isbeginde1: process (A, G1)beginif G1 = 1 theny1 Y1 Y1 Y1 Y1 Y1 = 1111;end case;end if;end process;de2: process (B, G2)beginif G2 = 1 thenY2 Y2 Y2 Y2 Y2 Y2 0); signal B : std_logic_vector(1 downto 0) := (others = 0); -Outputs signal Y1

14、: std_logic_vector(3 downto 0); signal Y2 : std_logic_vector(3 downto 0);BEGIN- Instantiate the Unit Under Test (UUT) uut: deceoder_beh PORT MAP ( G1 = G1, G2 = G2, A = A, B = B, Y1 = Y1, Y2 = Y2 ); - Stimulus process stim_proc: process begin - insert stimulus here G1 =1; WAIT FOR 100 ns; G1 =0; A =

15、 00; B = 00; - - - - Current Time: 200ns WAIT FOR 100 ns; G1 =0; A = 01; B = 01; - - - - Current Time: 300ns WAIT FOR 100 ns; G1 =0; A = 10; B = 10; - - - - Current Time: 400ns WAIT FOR 100 ns; G1 =0; a = 11; b = 11; WAIT FOR 100 ns; end process;END;测试波形如下：可以看到当G1=0和G2=0可以正常的译码，当G1=1和G2=1，则Y1和Y2都输出”

16、1111”。数据流代码如下：- Company: - Engineer: - Create Date: 23:14:31 12/02/2016 - Design Name: - Module Name: decoder_dataf - Behavioral - Project Name: - Target Devices: - Tool versions: - Revision: - Revision 0.01 - File Created- Additional Comments: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_L

17、OGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity decoder_dataf isPort ( G1,G2:in std_logic; A : in std_logic_vector(1 downto 0); B : in std_logic_vector

18、(1 downto 0); Y1 : out std_logic_vector(3 downto 0); Y2 : out std_logic_vector(3 downto 0);end decoder_dataf;architecture dataflow of decoder_dataf issignal G11,G22 :std_logic;signal A0,A1 :std_logic;signal B0,B1 :std_logic;beginG11 = not G1;G22 = not G2;A0 = not A(0);B0 = not B(0); A1 = not A(1); B

19、1 = not B(1); Y1(0) = not (G11 and A0 and A1); Y2(0) = not (G22 and B0 and B1); Y1(1) = not (G11 and A1 and (not A0); Y2(1) = not (G22 and B1 and (not B0); Y1(2) = not (G11 and A0 and (not A1); Y2(2) = not (G22 and B0 and (not B1); Y1(3) = not (G11 and (not A0) and (not A1); Y2(3) = not (G22 and (no

20、t B0) and (not B1);end dataflow;TestBench代码没有改变。可以看到与（1）中结论一致得到如下波形。结构描述代码如下：- Company: - Create Date: 12:01:26 12/03/2016 - Design Name: - Module Name: decoder_stuc - Behavioral - Project Name: - Target Devices: - Tool versions: - Description: - Dependencies: - Revision: - Revision 0.01 - File Crea

21、ted- Additional Comments: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.library UNISIM;use UNISIM.VComponents.all;entity decoder_stuc is PORT( G1

22、 : IN std_logic; G2 : IN std_logic; A : IN std_logic_vector(1 downto 0); B : IN std_logic_vector(1 downto 0); Y1 : OUT std_logic_vector(3 downto 0); Y2 : OUT std_logic_vector(3 downto 0) );end decoder_stuc;architecture struct of decoder_stuc issignal G11,G22 :std_logic;signal A0,A1 :std_logic;signal

23、 B0,B1 :std_logic;signal A00,A11 :std_logic;signal B00,B11 :std_logic;signal Y11 :std_logic_vector(3 downto 0);signal Y22 :std_logic_vector(3 downto 0);begin U0 : INV port map (A0, A(0);U1 : INV port map (B0, B(0);U2 : INV port map (G11, G1);U3 : INV port map (G22, G2);U4 : INV port map (A1, A(1);U5

24、 : INV port map (B1, B(1);U6 : INV port map (A00, A0);U7 : INV port map (B00, B0);U8 : INV port map (A11, A1);U9 : INV port map (B11, B1);U10: nand3 port map (Y11(0), A0, A1, G11);U11: nand3 port map (Y22(0), B0, B1, G22);U12: nand3 port map (Y11(1), G11, A1, A00);U13: nand3 port map (Y22(1), G22, B

25、1, B00);U14: nand3 port map (Y11(2), G11, A0, A11);U15: nand3 port map (Y22(2), G22, B0, B11);U16: nand3 port map (Y11(3), G11, A00, A11);U17: nand3 port map (Y22(3), G22, B00, B11); Y1 = Y11;Y2 = Y22;end struct;TestBench代码没有改变。可以看到与（1）中结论一致得到如下波形。Analyze and simulate the following code lists (code1

26、 and code 2) with the same input signals shown below by presenting POW and OL. If the data type of “a, b, c, d, u, v, w, x, y, z” is declared as std_logic, what changes the simulation outputs will be?Code 1:entity delta isport(a, b, c, d: in bit; u, v, w, x, y, z: buffer bit);end delta;architecture

27、ar_delta of delta isbeginz= not y;y= w or x;x= u or v;w= u and v;v= c or d;u= a and b;end ar_delta;Code 2:entity delta isport(a, b, c, d: in bit; u, v, w, x, y, z: buffer bit);end delta;architecture ar_delta of delta isbeginz= not y after 10 ns;y= w or x after 10 ns;x= u or v after 10 ns;w= u and v

28、after 10 ns;v= c or d after 10 ns;u a, b = b, c = c, d = d, u = u, v = v, w = w, x = x, y = y, z = z ); - Stimulus process stim_proc: process begin a =1;b =0;c =1;d =0; WAIT FOR 100 ns; a =1;b =0;c =0;d =0; WAIT FOR 100 ns; a =0;b =0;c =0;d =0; WAIT FOR 100 ns; a =0;b =0;c =0;d =1; WAIT FOR 100 ns;

29、a =0;b =1;c =0;d =1; WAIT FOR 100 ns; a =0;b =1;c =1;d =0; WAIT FOR 100 ns; a =1;b =1;c =1;d =0; WAIT FOR 100 ns; a =1;b =1;c =0;d =0; WAIT FOR 100 ns; a =0;b =0;c =0;d =1; WAIT FOR 100 ns;a =0;b =0;c =0;d 1. 0+4：y的动作发生在w、x之后，所以在w、x中有一个发生变化，那么下一个延时之后，y才动作：0-1. 0+5：z的动作发生在y之后，所以在y：0-1之后，下一个延时之后， z才动作

30、：1-0. 此时，在输入没有新的变化情况下，所有的输出信号都已经更新完毕。此后的时间，信号的更新分析方法同上面的分析。其中值得注意的一点就是，在每次输入信号变化的时候，这个变化在ModelSim中是有一个延时的。如下图所示：结论：输出的改变在输入的值改变之后发生，且延时决定于电路。本电路的输出与输入信号之间的延时关系：u比a、b延时一个.v比c、d延时一个.w比u、v延时一个 x比u、v延时一个.y比w、x延时一个.z比y延时一个. 分析：CODE2说明：code2的描述属于（Standard Time Unit Delay STUD）。该段代码与code1的主要区别就是在每条赋值语句之后添加

31、一个固定的延时10ns，这样便可以更清楚地观察信号之间的延时关系。譬如u在a或者b改变之后10ns作出反应，而w则在u改变10ns后作出跳变，也就是a, b变化20ns之后作出变化，关于这一点可以参考综合后的电路和对code1的分析。即w决定于a，b，c，d四个信号，而对于这几个信号的反应延时均为20ns。 分析LIST看到二者还是有区别的，例如在300ns时候，CODE1一个接一个时间下改变输出，而CODE2只在输入信号改变时候需要一个，后面不需要再使用，after 10ns代表了实际的延时输出，由于输入信号的变化引起的输出信号的每一次变化都需要10ns（被忽略）的延时证明了前面的输出影响到

32、了后面的输出，他们是有顺序的输出，分析与CODE1一样。区别只是CODE1是改变输出，而CODE2是10ns改变输出。（2）、将输入和输出的代码的类型改为std_logic，代码无大改动直接给出输出波形和LIST。CODE1和CODE2输出波形如下：CODE1 波形CODE2 波形 CODE1 LIST CODE2 LIST 分析CODE1：观察输出波形bit与std_logic两种类型结果一样，对比bit和std_logic两种类型的list表，我们发现，它们的延时效果是一样的。只是std_logic类型在初始赋值阶段的输出有Unknown的情况。分析CODE2：和bit数据类型最大的不同就

33、是在a，b，c，d的数据值确定之前，u，v等数据为红色表示，即不确定状态UUnknown。在输入的a，b等值确定之前，x，y，z 等数值不能确定，根据std_logic的九值逻辑原则，此时的输出值为Unknown。但是，每过一个10ns的延时，就会有一个输出从Unknown状态变化为其他状态。经过40ns后，输出随输入信号的变化和前面分析的一样。（3）、总结： 通过code1和code2的比较以及将代码中的bit数据类型转化为std_logic类型后比较可以得到以下结论：1、数据类型std_logic是九值逻辑，相对bit数据类型多了U、X等数据类型，在信号被赋值以前，std_logic和bit数据类型的不同就表现出来了；2、仿真延时单元是硬件描述中的基本时间单位，每一个延时以及反应过程都是以为单位进行的。譬如赋值语句后，在没有延时操作的情况下，系统至少经过一个才能将值传给信号；3、在前仿真中，当使用标准时间单元延时（Standard Time Unit Delay），即“after 10ns”等操作存在时，将被忽略，因为经过了一个大