smic13_ICC_flow_Allen

1、SMIC13 ICC Flow Introduction to DevelopersAllen.YangXmartThe IC design backend training item list IC compiler training overviewICC and P&R flow overviewPV tool calibre overviewPV DRC/LVS flow overviewSTA PrimeTime overviewStarRCXT tool overview IC Compiler is an integral part of the Synopsys Galaxy

2、Implementation Platform that delivers a comprehensive design solution, including synthesis, physical implementation, low-power design, and design for manufacturability.IC Compiler is a single, convergent, chip-level physical implementation tool that includes flat and hierarchical design planning, pl

3、acement and optimization, clock tree synthesis, routing, manufacturability, and low-power capabilities that enable designers to implement todays high-performance, complex designs on schedule.IC Compiler overview Comprehensive Place and Route SystemMulticore support for higher throughput for designs

4、in mainstream silicon technologiesHigh performance for advanced silicon technologiesComprehensive optimization capabilities meet timing, area, power, signal integrity, routability and manufacturing objectivesPredictability during the implementation processSingle timerComplete netlist-to-GDSII soluti

5、on for best QoR and TTRICC advanced featuresThe typical flow of the IC design andPhysical implementationThe IC design RoadmapSYNOPSYS flow toolsUsage mapThe Partition flowIn Cadence tools The general flow of ICC P&RData setupfloorplanningplacementCTSRoutingChip Finishing/ExportNetlist SDC UPF techfi

6、le .dbSetup the Virable Target_library Link_libraryRefrence_library and create the Milkyway library, read in the verilog netlist and link the design with the .dbLoad the UPF after the netlist readCreate_mw_libRead_verilogLoad_upf Link -force Set_min_librarySet_operating_conditionsSet_tlu_plus_filesC

7、heck_mv_design The general flow of ICC floorplanData setupfloorplanningplacementCTSRoutingChip Finishing/ExportNetlist SDC UPF techfile .dbCreate_floorplanThen for groupsCreate_plan_groupsCreate_fp_plan_group_paddingCreate_fp_placementShape_fp_blocksCommit_fp_plan_groupsCreate_power_strapsAdd_tap_ce

8、ll_arrayIf LOW_POWER enabled thenCreate_voltage_areaAdd_power_switchDerive_pg_connectionPreroute_standard_cellsThe general flow of ICC place_optData setupfloorplanningplacementCTSRoutingChip Finishing/ExportNetlist SDC UPF techfile .dbSource $SDCSet_host_options max_cores 6Place_opt -effort high con

9、gestion power area_recoveryPsynopt -area_recovery power -congestion The general flow of ICC CTSData setupfloorplanningplacementCTSRoutingChip Finishing/ExportNetlist SDC UPF techfile .dbRemove_clock_treeSet_delay_calculationDefine_routing_ruleSet_clock_tree_referenceSet_clock_tree_optionsSet_ignored

10、_layer max Metal6Clock_opt -only_cts -no_clock_routeSet_propagated_clock get_clocks *Extract_rc -estimatePsynopt congestion area_recoveryThe general flow of ICC RouteData setupfloorplanningplacementCTSRoutingChip Finishing/ExportNetlist SDC UPF techfile .dbSet_si_optionsSet_route_mode_optionsSet_rou

11、te_zrt_detail_optionsSource $antenna_ruleRoute_zrt_group -all_clock_netsExtact_rcRoute_opt effort high xtalk powerInsert_zrt_redundant_viasInsert_stdcell_fillerVerify_zrt_routeRoute_zrt_ecoThe general flow of ICC exportData setupfloorplanningplacementCTSRoutingChip Finishing/ExportNetlist SDC UPF te

12、chfile .dbChange_names rules verilog -hierWrite_verilogSet_write_stream_options Write_streamICC floorplan methodICCEncounterDEFThe DEF exchange flooplan and Preroute information only save time for Edit Power, less iteration there between toolsSolve the discrepancy between ICC and encounter When we s

13、tart the place_opt in ICC_shell, we need add the command below here , this command force the preroute to be dont touch set_attribute get_net_shape -f “route_type = signal_route ” route_type user_enterPhysicalVerification tools of CalibreCalibres physical verification capabilities are the industry st

14、andard for accuracy, reliability, and performance.Calibre nmDRCandCalibre nmLVSare the market share leaders in physical verification. Calibre also leads the market with innovative features such as incremental DRC, which ensures you can complete your design rule checking quickly and efficiently, and

15、equation-based design rules, which let designers define continuous, three-dimensional functions that accurately and precisely reflect the complex physical interactions of todays nanometer designs.Layout verification after ICCThe LVS calibre flow introductionThe DRC calibre flow introductionThe outpu

16、t from ICC after chip finish2022/7/1520DRC runset examplecommand：calibre -drc -hier runset2022/7/1521Calibre LVS runset examplev2lvs -v MY_CHIP_LVS.v -l tsmc18_lvs.v -o MY_CHIP_PAD.spi -s tsmc18_lvs.spi V2lvs transfer Netlist to Spice Netlistcalibre -lvs -spice layout.spi -hier -auto RUNSETPrimeTime

17、 overviewThe Synopsys PrimeTime suite includes PrimeTime, PrimeTime SI, PrimeTime PX and PrimeTime VX. Anchored by the most trusted and advanced static timing signoff solution for gate-level designs, the PrimeTime suite offers comprehensive signal integrity analysis, statistical timing analysis and

18、full chip power analysis in a single integrated environment.Key benefits of PrimeTimeHSPICE-Accurate Results Minimize Over-DesignIntegrated Design Environment Improves ProductivityFast Turn-around Time Speeds Analysis and SignoffHigh Capacity Approach Reduces Hardware CostsComplete Solution Ensures

19、Comprehensive SignoffPrimeTime STA flow use .sdfPrimeTime ECO flowSNPS StarRC tool overviewStarRC is the EDA industrys gold standard for parasitic extraction. A key component of Synopsys Galaxy Implementation Platform, it provides a silicon-accurate and high-performance extraction solution for SoC,

20、custom digital, analog/ mixed-signal (AMS) and memory IC designs. StarRC is modeling of advanced physical needed for leading-edge process technologies, including 20-nm, 14-nm and beyond. Its seamless integration with industry standard digital and custom implementation systems, timing, signal integrity, power, physical verification and circuit simulation flows delivers unmatched ease-of-use and productivity to speed design closure and signoff verification.StarRC tools benefitsFoundry gold standard for extraction accuracy with broadest qualification and adoptionLeader in 20-nm and below pro