Lattice FPGA基础培训

1、Copyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -1Embargoed Until May 29th 2007Lattice FPGA Basic TrainingqBasic FPGA PricinplesqIspLever demoqLattice Differentiated ProductsCopyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -2Embargoed Until May 29th 2007Non-Volatile FP

2、GAsLow-Cost FPGAsSystem FPGAsMixed Signal PLDs Mainstream FPGA Features/Performance at Lower Cost DDR/DDR2 Full-Featured DSP SERDES Differentiated Architectures Power and Clock Management Eliminates Discrete Components & Lowers Risk Via Programmability Differentiated Technology with Substantial Desi

3、gn Benefits Design Security Instant-On Seamless Field Upgrades One-Chip Solution Full System-level Solution for Communications Applications World Class SERDES Embedded Hard IPLattice Differentiated ProductsCopyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -3Embargoed Until May 29th 200

4、7True Non-Volatile (NV) FPGA AdvantagesTraditionalFPGAHybrid NVFPGATrue NVFPGA Flexible Logic Flexible Logic Smaller Footprint Moderate Security Flexible Logic Smallest Footprint Highest Security Instant-onDesigners Prefer Non-Volatile FPGAsProvided They are Priced Competitively Copyright Lattice Se

5、miconductor 2007Introducing LatticeXP2 Page -4Embargoed Until May 29th 20073rd Generation Flash-based FPGAsYear200220052007Technology180nm EE130nm Flash90nm FlashMax Density15K LUTs20K LUTs40K LUTsPerformance122.5Relative Price1021InnovationNV + SRAM FPGALow CostLive Update & User FlashCopyright Lat

6、tice Semiconductor 2007Introducing LatticeXP2 Page -5Embargoed Until May 29th 2007Industry Leading 90nm Non-Volatile FPGAqTrue 90nm Flashq50% Lower Cost/LUTq2X Densityq33% Less Power/LUTqflexiFLASH 1mS Instant-on Single chip Highest security On-die user FlashqEnhanced Live UpdateCopyright Lattice Se

7、miconductor 2007Introducing LatticeXP2 Page -6Embargoed Until May 29th 2007LatticeXP2 ArchitectureJTAG & SPI PortssysCLOCK PLLs Frequency Synthesis-Up to 4 per deviceEnhanced Configuration Logicincludes Dual Boot, Decryption & TransFRPre-EngineeredSource SynchronousSupport:DDR2 400MbpsGeneric 750Mbp

8、sOn-Chip OscillatorFlashFlexible sysIO Buffers: LVCMOS, HSTL,SSTL, LVDS, + DSP BlocksMultiply and Accumulate Support ForUp to 32 18X18 MultiplierssysMEM Block RAM 18Kbit Dual PortUp to 885KbitsProgrammable Function Units (PFUs) Up to 40K LUTsFlexible Routing Optimized for Speed, Cost and Routability

9、Copyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -7Embargoed Until May 29th 2007High Performance sysDSP BlockXX+- XX+- + sysDSP Block+FFTX+XFilteringX XDUC+XXIQDDCCopyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -8Embargoed Until May 29th 2007LatticeXP2 PerformanceEleme

10、ntPerformancePFU375MHz*sysCLOCK PLL Input Range10 420MHzGlobal Clock500MHzsysMEM EBR350MHzsysDSP Block325MHzsysIO Buffer400Mbps (DDR1/2 memory)750Mbps (Generic DDR)Performance Supports Designs In Excess of 325MHz* Simple functions (For example 16-bit decoder, 16-bit counter)Copyright Lattice Semicon

11、ductor 2007Introducing LatticeXP2 Page -9Embargoed Until May 29th 2007Integrate Instant-On FunctionsInstant-On ApplicationsqPlug & Play Bus Interfaces PCI, PCI Express, CANqPower-on-Reset ControlqProcessor Bus DecodeqFPGA Loaders qASIC InitializationqLow Power Designs Using Duty CyclingBoot-up Over

12、50 x Faster With LatticeXP2020406080100120140LatticeXP2(17K LUTs)90nm Hybrid NV FPGAWake-Up Time (mS)Copyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -10Embargoed Until May 29th 2007Highest Design Securityq Data Stored On Chip In Flash Practically impossible to readq Optional Security

13、 Bits Prevent read back of Flash and SRAMq Optional 128-bit AES Programming Data Encryption Key stored in on chip Flashq 64-bit Flash Lock Prevents accidental or unauthorized reprogrammingq One Time Programmable (OTP) Mode Prevents any further erasure or programmingCopyright Lattice Semiconductor 20

14、07Introducing LatticeXP2 Page -11Embargoed Until May 29th 2007FlashBAK Technology q Use FlashBAK to Store:Error Codes, POST Results, Serial Numbers and uP Codeq Erase and Reprogram Flash in 10 seconds q sysMEM EBR 166 to 885Kbitsq Unlimited Random Read and Write Capability through EBRFlashFPGALogicE

15、BRJTAG / SPIPORTWrite From Flash to EBRs During Configuration /Write From EBRs to Flash on User CommandMake Infinite Reads & Writes to EBR Speeds of up to 350MHzWrite to Flash During Programming Copyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -12Embargoed Until May 29th 2007Serial TA

16、G Memoryq Use TAG Memory to Store: Electronic ID Code Version Code Date Stamp Asset ID Calibration Settings q TAG Memory Outside of SecurityData Shift Register FlashMemoryArrayJTAGFPGA LogicJTAGSequentialAddresscounterSpecifyStartAddressFPGA LogicTDOTDIDeviceTAG Memory (KBits)XP2-50.6XP2-80.7XP2-172

17、.2XP2-302.6XP2-403.4Copyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -13Embargoed Until May 29th 2007Comprehensive Remote Update SolutionRequirementsq Reliabilityq Maximum Up Timeq SecurityLatticeXP2q Dual Bootq TransFRq 128-bit AES EncryptionCopyright Lattice Semiconductor 2007Introd

18、ucing LatticeXP2 Page -14Embargoed Until May 29th 2007Live Update With TransFR TechnologyField Update FPGAs and Maintain High System UptimeStep 1Load New Config. To Configuration MemoryStep 2Lock The I/Os In The Desired StateStep 3Apply New ConfigurationStep 4FPGA Regains Control of I/OFLASH(Configu

19、ration 2)Logic SRAM(Configuration 1)FLASH(Configuration 2)Logic SRAM(Configuration 1)FLASH(Configuration 2)Logic SRAM(Configuration 2)FLASH(Configuration 2)Logic SRAM(Configuration 2)Copyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -15Embargoed Until May 29th 2007Reliable Update With

20、Dual Boot q Golden Configuration Stored in SPI Memoryq LatticeXP2 Will Automatically Use Backup (Golden) Configuration if Active Configuration is Invalidq Guarantees FPGA Operation if Update FailsRead DataControlSPI Configuration MemoryBackup (Golden)ConfigurationFLASH(Configuration 1)LogicFLASH(Con

21、figuration 2)FLASH(Configuration 1)FLASH(Configuration 1)FLASH(Configuration 2)Active FLASHConfigurationLOGIC SRAMLatticeXP2 Loads Active Configuration at Power Up If Error Detected in Active Configuration Then Backup (Golden) Configuration is Loaded From SPI Flash Copyright Lattice Semiconductor 20

22、07Introducing LatticeXP2 Page -16Embargoed Until May 29th 2007 DeviceXP2-5XP2-8XP2-17XP2-30XP2-40LUTs (K)58172940EBR SRAM Blocks912152148EBR SRAM (Kbits)166221276387885Distributed RAM (Kbits)1018355683# 18x18 Multipliers1216202832PLLs22444Package & IO Combinations132-ball csBGA (8x8mm)8686144-pin TQ

23、FP (20 x20mm)100100208-pin PQFP (28x28mm)146146146256-ball ftBGA (17x17mm)172201201201484-ball fpBGA (23x23mm)358363363672-ball fpBGA (27x27mm)472540LatticeXP2 FamilyFull Array of Packages & I/O at Each Density PointCopyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -17Embargoed Until M

24、ay 29th 2007Lattice Low Cost FPGA Road Map Up to 33K LUTs 400Mbps DDR 10 GMAC DSP SPI Boot Memory 2X Density Increase 50% I/O Speed Increase 3X DSP Performance Enhanced Configuration ECP2 Architecture 16 SERDES (3.125Gbps) 5X RAM Increase 2X DSP Performance 30% More LUTs90nm90nm130nmCopyright Lattic

25、e Semiconductor 2007Introducing LatticeXP2 Page -18Embargoed Until May 29th 2007LatticeECP2/M Key Featuresq Low Cost FPGA 6K to 95K LUT4s 12K to 202K bits distributed RAM Up to 601 I/Oq Embedded 3.125Gbps SERDES* Up to 16 channels Supports PCI Express, Ethernet (1GbE, & SGMII) plus related standards

26、q Full Featured sysDSP Blocks Up to 168 18x18 multipliersq Up to 5.3Mbit Block RAMq High Performance sysIOTM Buffers DDR1 and DDR2 SPI4.2 and ADC/DAC interfaces LVCMOS 33/25/18/15/12, LVDS, PCIq sysCLOCKTM PLLs & DLLsq Dual boot, TransFR and Encryption* SERDES only available on ECP2M versionsCopyrig

27、ht Lattice Semiconductor 2007Introducing LatticeXP2 Page -19Embargoed Until May 29th 2007LatticeECP2/M ArchitectureConfiguration PortProgrammable Function Units Up to 95K LUTs 3.125 Gbps SERDESPCI Express, 1GbE, SGMII & GenericDSP BlocksMultiply & Accumulate Up to 168 18x18 MultsysCLOCK GPLLs & GDLL

28、sFrequency Synthesis & Clock AlignmentConfigurationDual Boot, Encryption & Transparent UpdatesFlexible RoutingOptimized for Speed, Cost and Routability Pre-Engineered Source Synchronous I/O DDR2 400MbpsSPI4.2 750Mbps Generic 840MbpsOn-chip OscillatorFlexible sysIO LVCMOS, HSTL, SSTL, LVDS, +Up to 60

29、1 I/OsysCLOCK SPLLssysMEM Block RAM 18kbit Dual PortUp to 5.3 MbitNote: ECP2M Architecture Shown. ECP2 Similar But Contains No SERDES.Copyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -20Embargoed Until May 29th 2007Extensive High Performance ClockingqHigh Performance Clock Distributio

30、n Eight global clock networks Eight regional secondary clocks Two low-skew edge clocks per sideqsysCLOCK PLL and DLL Technology 2 to 8 PLLs per device External capacitor allows operation as low as 1MHz Dynamic phase shift capability 2 DLLs per deviceqOn-Chip Oscillator (2.5 to 130MHz)qEdge Clock Div

31、ider X2, X4, X8 For high speed source synchronous implementationsCopyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -21Embargoed Until May 29th 2007q Low Cost SERDESChip to chipSmall form factor backplanesIdeally suited for low cost systemsq Up to 16 Channels per Deviceq Data Rates from

32、 540Mbps to 3.125 Gbps Half Rate Mode Allows Operation at 270Mbps q Supports Key Serial Standards Ethernet: GbE, SGMII PCI Express Serial RapidIO, OBSAI/CPRI q TX Pre-Emphasis (4 settings: 0%, 16%, 32%, 48%) and RX Equalization (3 settings: short, medium, long) Improves Backplane Performance Operate

33、 over 20 inches of FR4 at 3.125Gbpsq High Rx Jitter Tolerance (0.8UI Typical 2.5Gbps)q Low Tx Jitter (0.25UI Typical 2.5 Gbps) q Very Low Power (100mW Per Channel Typical 2.5Gbps)LatticeECP2M SERDES Copyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -22Embargoed Until May 29th 2007Latti

34、ceECP2M PCS: Supported Packet ProtocolsLatticeECP2M SERDESTx RxTx RxTx RxTx Rx8b/10b8b/10bRx LinkSynchronize8b/10bGbE StateMach/Auto-NegotiationClockToleranceComp8b/10bCRCPCIExpressSerialRapidIOGigabitEthernet*FibreChannelRx LinkSynchronizeRx LinkSynchronizeRx LinkSynchronizeClockToleranceCompEOFDis

35、parityHandlingPCIe PHY Soft LogicChannel AlignmentClock Tolerance CompensationFramingLTSSMState MachineSoft LogicChannel AlignmentRX State MachineClock Tolerance CompensationSGMII(Optional)SupportedPHYsEmbeddedSERDESAndPhysicalCodingSub Layers(PCS)Soft IP* CPRI/OBSAI Supported By ExtensionCopyright

36、Lattice Semiconductor 2007Introducing LatticeXP2 Page -23Embargoed Until May 29th 2007LatticeECP2M Complete PCI Express SolutionIPexpress Allows Simple GUI BasedSERDES ConfigurationECP2M PCI Express Plug-in Evaluation CardPlug and Play Card In Standard PC Chassisq Integrated Hardware: SERDES + Low C

37、ost FPGA on One Chipq Intellectual Property: Lattice Supplied PCI Express X1 and X4 Coresq Easy To Use: GUI-based Configuration of PCI Express X1 and X4 q Demo Board: PC Motherboard PCI Express Plug-in Card q Software Drivers: Provide Starting Point for System Level Integrationq Lowest Implementatio

38、n CostCopyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -24Embargoed Until May 29th 2007High-Performance sysDSP Blockq Programmable Multiplier 1 36x36 or 4 18x18 or 8 9x9q Programmable Addition, Subtraction & Accumulateq Programmable Pipelining Input / Intermediate / Outputq 375MHz Per

39、formance Provides up to 63 GMAC/second per deviceq ECP2M SERDES Allows Easy Distribution of Dataq Suitable for Wide Range of DSP Functions Including FIR Filters, FFTs and complex arithmetic XX+- XX+- + sysDSP BlockCopyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -25Embargoed Until May

40、 29th 2007DQS/Strobe Delay and Transition Detect*PIO ATri-stateRegister Block(2 Flip/flops)InputPICPre-Engineered Source Synchronous I/Oq Implement High Speed Memory Interfaces DDR1 (400Mbps) DDR2 (400Mbps)q Implement High Speed Source Synchronous Interfaces SPI4.2 (750Mbps) Generic (840Mbps)q Pre-E

41、ngineered I/O Logic Support DDR to SDR Conversion Gearbox logic DQS/Strobe AlignmentDDR to SDR ConversionOutputRegister Block(2 Flip/flops)InputRegister Block(5 Flip/flops)PIO B (Detail Not Shown)* SelectedBlocks2:1 Gearbox(Optional) Shared With PIO BPrecision Strobe/DQS Alignment2:1 Gearbox for Ope

42、ration Up to 840MbpsCopyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -26Embargoed Until May 29th 2007Advanced Configuration SupportqFlexible Configuration Options Low-cost SPI boot memory, microprocessor, JTAGqEncryption Bit Stream On-chip 128-bit AES decryption Encryption key securel

43、y stored on-chipqAutomatic SPI Dual Boot Allows recovery if power or communication fails during field updateqSimple Field Configuration Define I/O state during field configuration Reconfigure FPGA while system operatesCopyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -27Embargoed Until

44、 May 29th 2007Encryption Overviewq Design Security Increasingly Important Overbuilding, reverse engineering and cloning all too commonq Optionally Encrypt Bitstreams With 128-bit AES Encryption Using ispLEVERq On-Chip OTP Fuses Store 128-bit Decryption Keyq On-Chip 128-bit AES Decryption EngineConfi

45、guration Memory128-bit AES Encrypted BitstreamLatticeECP2/MDecryptionEngine128-bit KeyKey Stored In OTP FusesDecrypted Data Configures FPGACopyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -28Embargoed Until May 29th 2007Dual Boot Modeq Store Active and Backup (Golden) Configurations I

46、n SPI Configuration Memoryq LatticeECP2/M Will Automatically Use Golden Configuration If Active Configuration is Invalidq Increase System Reliability When Configurations are Field UpdatedSector 0Sector 1Read DataControlLatticeECP2/MLatticeECP2/M Loads Active Configuration (B) at Power Up. If This Fa

47、ils Configuration A is UsedSPI Configuration MemoryGolden (A)ConfigurationActive (B)Configuration Copyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -29Embargoed Until May 29th 2007LatticeECP2/M PerformancePerformance Supports Designs In Excess of 350MHz* Simple functions (For example 1

48、6-bit decoder, 16-bit counter)* ECP2M OnlyElementPerformance (MHz)PFU/PFF375Mz*sysCLOCK PLL Input Range2 - 420 MHzGlobal Clock500 MHzsysMEM EBR370 MHzSERDES*270 Mbps to 3.125 GbpssysDSP Block375 MHz400 Mbps (DDR Memory)800 Mbps (Generic DDR )sysIO Buffer750 Mbps (SPI4.2)Copyright Lattice Semiconduct

49、or 2007Introducing LatticeXP2 Page -30Embargoed Until May 29th 2007Extensive IP Supportq PCI Express (X1 & X4)q SGMIIq PCIq SPI4.2q DDR1 / 2 q Tri-speed Ethernet MAC q 10Gb Ethernet MACq OBSAIq CPRIq LatticeMico32 Microprocessorq FIR Compilerq FFT Compilerq Correlatorq NCO q Turbo Encoder/Decoderq C

50、onvolution Encoder (OFDM)q RS Encoder/Decoder (OFDM) q Viterbi Decoder (OFDM)q CIC Filterq Interleaver / De-Interleaverq CORDICq Color Space Converter (CSC)Copyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -31Embargoed Until May 29th 2007LatticeEC / ECP2 / ECP2M Families1st Device Devi

51、ceECECP2ECP2M136122035507020355070100 LUTs (K)1.53612213248681934486795 18x18 Multipliers-12242832728824328896168 Distributed RAM (Kbits)61212244265961364171101145202 EBR SRAM Blocks263121518216066114225246288 EBR Block SRAM (Kbits)185555221276332 387 11061217 2101 414745345308 PLLs/DLLs2/02/02/22/2

52、2/22/24/26/28/28/28/28/28/2 DDR Memory (Mbps)400 400400 400400400 400 400400400400400400 Package I/O I/O I/O/SERDES 100-pin TQFP (14x14mm)6767 144-pin TQFP (20 x20mm)97979093 208-pin PQFP (28x28mm)112 145131131 256-ball fpBGA (17x17mm)160190 1931934/144 TBD 484-ball fpBGA (23x23mm)297331331 3394/301

53、 4/301 4/287 672-ball fpBGA (27x27mm)402450 500 5004/411 8/387 900-ball fpBGA (31x31mm)5888/457 16/44916/457 1156-ball fpBGA (35x35mm)16/601 AvailabilityNow NowNov06NowNov06Nov06NowDec061Q07Oct062Q 072Q073Q07Full Range of EConomy Plus FPGAsCopyright Lattice Semiconductor 2007Introducing LatticeXP2 P

54、age -32Embargoed Until May 29th 2007引文引文q旨在于探讨可编程逻辑设计的一些基本规律。旨在于探讨可编程逻辑设计的一些基本规律。FPGA/CPLD的设计规律与方法是一个非常大的论的设计规律与方法是一个非常大的论题，在此不可能面面俱到，希望通过本章提纲携领题，在此不可能面面俱到，希望通过本章提纲携领地粗浅介绍，引起读者们的注意，如果大家能在日地粗浅介绍，引起读者们的注意，如果大家能在日后的工作实践中，不断积累，有意识的用后的工作实践中，不断积累，有意识的用FPGA/CPLD的基本设计原则、设计思想作为指导的基本设计原则、设计思想作为指导，将取得事半功倍的效果！，

55、将取得事半功倍的效果！ Copyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -33Embargoed Until May 29th 2007Agendaq面积与速度的平衡与互换原则面积与速度的平衡与互换原则 面积与速度的平衡与互换原则提出了面积与速度的平衡与互换原则提出了FPGA/CPLD设计的设计的2个基本目个基本目标，并探讨了这两个目标的对立统一的矛盾关系。标，并探讨了这两个目标的对立统一的矛盾关系。q硬件原则硬件原则 硬件原则重点在于提醒读者转化软件设计的思路，理解硬件原则重点在于提醒读者转化软件设计的思路，理解

56、HDL语言设语言设计的本质。计的本质。q系统原则系统原则 系统原则希望读者能够通过全局上、整体上把握设计，从而提高设系统原则希望读者能够通过全局上、整体上把握设计，从而提高设计质量，优化设计效果。计质量，优化设计效果。q同步设计原则同步设计原则 同步设计原则是设计时序稳定的基本要求，也是高速同步设计原则是设计时序稳定的基本要求，也是高速PLD设计的通设计的通用法则。用法则。 Copyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -34Embargoed Until May 29th 2007面积与速度的互换原则面积与速度

57、的互换原则q面积（面积（Area）和速度（）和速度（Speed）这两个指标贯穿着）这两个指标贯穿着FPGA/CPLD设计的始终，是设计质量评价的终极标准；设计的始终，是设计质量评价的终极标准；q面积和速度是一对对立统一的矛盾体。要求一个设计同时面积和速度是一对对立统一的矛盾体。要求一个设计同时具备设计面积最小，运行频率最高是不现实的。更科学的具备设计面积最小，运行频率最高是不现实的。更科学的设计目标应该是在满足设计时序要求（包含对设计最高频设计目标应该是在满足设计时序要求（包含对设计最高频率的要求）的前提下，占用最小的芯片面积。或者在所规率的要求）的前提下，占用最小的芯片面积。或者在所规定的面

58、积下，使设计的时序余量更大，频率跑得更高。这定的面积下，使设计的时序余量更大，频率跑得更高。这两种目标充分体现了面积和速度的平衡的思想两种目标充分体现了面积和速度的平衡的思想 ；q关于面积和速度的要求，我们不应该简单的理解为工程师关于面积和速度的要求，我们不应该简单的理解为工程师水平的提高和设计完美性的追求，而应该认识到它们是和水平的提高和设计完美性的追求，而应该认识到它们是和产品的质量和成本直接相关的。如果设计的时序余量比较产品的质量和成本直接相关的。如果设计的时序余量比较大，运行的频率比较高，则意味着设计的健壮性更强，整大，运行的频率比较高，则意味着设计的健壮性更强，整个系统的质量更有保证

59、；另一方面，设计所消耗的面积更个系统的质量更有保证；另一方面，设计所消耗的面积更小，则意味着在单位芯片上实现的功能模块更多，需要的小，则意味着在单位芯片上实现的功能模块更多，需要的芯片数量更少，整个系统的成本也随之大幅度削减芯片数量更少，整个系统的成本也随之大幅度削减 。Copyright Lattice Semiconductor 2007Introducing LatticeXP2 Page -35Embargoed Until May 29th 2007面积与速度的互换原则面积与速度的互换原则q 作为矛盾的两个组成部分，面积和速度的地位是作为矛盾的两个组成部分，面积和速度的地位是不一样的

60、。相比之下，满足时序、工作频率的要不一样的。相比之下，满足时序、工作频率的要求更重要一些，当两者冲突时，采用速度优先的求更重要一些，当两者冲突时，采用速度优先的准则准则 ；q 从理论上讲，一个设计如果时序余量较大，所能从理论上讲，一个设计如果时序余量较大，所能跑的频率远远高于设计要求，那么就能通过功能跑的频率远远高于设计要求，那么就能通过功能模块复用减少整个设计消耗的芯片面积，这就是模块复用减少整个设计消耗的芯片面积，这就是用速度的优势换面积的节约；用速度的优势换面积的节约；q 反之，如果一个设计的时序要求很高，普通方法反之，如果一个设计的时序要求很高，普通方法达不到设计频率，那么一般可以通过