AD0809数据手册

1、June 1999ADC0808/ADC08098-Bit µP Compatible A/D Converters with 8-ChannelMultiplexerGeneral DescriptionThe ADC0808, ADC0809 data acquisition component is amonolithic CMOS device with an 8-bit analog-to-digital con-verter, 8-channel multiplexer and microprocessor compatiblecontrol logic. The 8-b

2、it A/D converter uses successive ap-proximation as the conversion technique. The converter fea-tures a high impedance chopper stabilized comparator, a256R voltage divider with analog switch tree and a succes-sive approximation register. The 8-channel multiplexer candirectly access any of 8-single-en

3、ded analog signals.The device eliminates the need for external zero andfull-scale adjustments. Easy interfacing to microprocessorsis provided by the latched and decoded multiplexer addressinputs and latched TTL TRI-STATE ® outputs.The design of the ADC0808, ADC0809 has been optimizedFeaturesn E

4、asy interface to all microprocessorsn Operates ratiometrically or with 5 VDC or analog spanadjusted voltage referencen No zero or full-scale adjust requiredn 8-channel multiplexer with address logicn 0V to 5V input range with single 5V power supplyn Outputs meet TTL voltage level specificationsn Sta

5、ndard hermetic or molded 28-pin DIP packagen 28-pin molded chip carrier packagen ADC0808 equivalent to MM74C949n ADC0809 equivalent to MM74C949-1Key Specificationsby incorporating the most desirable aspects of several A/Dconversion techniques. The ADC0808, ADC0809 offers highspeed, high accuracy, mi

6、nimal temperature dependence, ex-cellent long-term accuracy and repeatability, and consumesminimal power. These features make this device ideallysuited to applications from process and machine control tonnnnnResolutionTotal Unadjusted ErrorSingle SupplyLow PowerConversion Time8 Bits± 12 LSB and

7、 ±1 LSB5 VDC15 mW100 µsconsumer and automotive applications. For 16-channel mul-tiplexer with common output (sample/hold port) seeADC0816 data sheet. (See AN-247 for more information.)Block DiagramDS005672-1See OrderingInformationTRI-STATE® is a registered trademark of National Semico

8、nductor Corp.© 1999 National Semiconductor CorporationDS005672ADC0808/ADC0809 8-Bit µP Compatible A/D Converters with 8-Channel MultiplexerConnection DiagramsMolded Chip Carrier PackageDual-In-Line PackageDS005672-12DS005672-11Order Number ADC0808CCN or ADC0809CCNSee NS Package J28A or N28

9、AOrdering InformationOrder Number ADC0808CCV or ADC0809CCVSee NS Package V28ATEMPERATURE RANGE40C to +85C55C to +125CError± 12 LSB UnadjustedADC0808CCNADC0808CCVADC0808CCJADC0808CJ±1 LSB UnadjustedADC0809CCNADC0809CCVPackage OutlineN28A Molded DIPV28A Molded Chip CarrierJ28A Ceramic DIPJ28

10、A Ceramic DIP2Absolute Maximum Ratings (Notes 2, 1)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage (VCC) (Note 3) 6.5VVoltage at Any Pin 0.3V to (VCC+0.3V)Except Control Inputs

11、Voltage at Control Inputs 0.3V to +15V(START, OE, CLOCK, ALE, ADD A, ADD B, ADD C)Storage Temperature Range 65C to +150CPackage Dissipation at TA=25C 875 mWDual-In-Line Package (ceramic)Molded Chip Carrier PackageVapor Phase (60 seconds)Infrared (15 seconds)ESD Susceptibility (Note 8)Operating Condi

12、tionsTemperature Range (Note 1)ADC0808CCN,ADC0809CCNADC0808CCV, ADC0809CCVRange of VCC (Note 1)300C215C220C400V(Notes 1, 2)TMINTATMAX40CTA+85C40C TA +85C4.5 VDC to 6.0 VDCLead Temp. (Soldering, 10 seconds)Dual-In-Line Package (plastic) 260CElectrical CharacteristicsConverter Specifications: VCC=5 VD

13、C=VREF+, VREF()=GND, TMINTATMAX and fCLK=640 kHz unless otherwise stated.SymbolParameterConditionsMinTypMaxUnitsADC0808Total Unadjusted Error(Note 5)25CTMIN to TMAX± 12± 34LSBLSBADC0809Total Unadjusted Error(Note 5)0C to 70CTMIN to TMAX±1±114LSBLSBInput ResistanceAnalog Input Vol

14、tage RangeFrom Ref(+) to Ref()(Note 4) V(+) or V()1.0GND0.102.5VCC+0.10kVDCVREF(+)Voltage, Top of LadderVoltage, Center of LadderMeasured at Ref(+)VCC/2-0.1VCCVCC/2VCC+0.1VCC/2+0.1VVVREF()Voltage, Bottom of LadderMeasured at Ref()0.10VIINComparator Input Currentfc=640 kHz, (Note 6)2±0.52µA

15、Electrical CharacteristicsDigital Levels and DC Specifications: ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75VCC5.25V,40CTA+85C unless otherwise notedSymbolParameterConditionsMinTypMaxUnitsANALOG MULTIPLEXERIOFF(+)OFF Channel Leakage CurrentVCC=5V, VIN=5V,IOFF()OFF Channel Leakage CurrentT

16、A=25CTMIN to TMAXVCC=5V, VIN=0,102001.0nAµATA=25CTMIN to TMAX2001.010nAµACONTROL INPUTSVIN(1)VIN(0)Logical “1” Input VoltageLogical “0” Input VoltageVCC1.51.5VVIIN(1)Logical “1” Input CurrentVIN=15V1.0µA(The Control Inputs)IIN(0)Logical “0” Input CurrentVIN=01.0µA(The Control Inp

17、uts)ICCSupply CurrentfCLK=640 kHz0.33.0mADATA OUTPUTS AND EOC (INTERRUPT)VOUT(1)Logical “1” Output VoltageIO=360 µAVCC0.4V3Electrical Characteristics(Continued)Digital Levels and DC Specifications: ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75VCC5.25V,40CTA+85C unless otherwise notedS

18、ymbolParameterConditionsMinTypMaxUnitsDATA OUTPUTS AND EOC (INTERRUPT)VOUT(0)VOUT(0)IOUTLogical “0” Output VoltageLogical “0” Output Voltage EOCTRI-STATE Output CurrentIO=1.6 mAIO=1.2 mAVO=5VVO=030.450.453VVµAµAElectrical CharacteristicsTiming Specifications VCC=VREF(+)=5V, VREF()=GND, tr=

19、tf=20 ns and TA=25C unless otherwise noted.SymboltWStWALEtstHtDParameterMinimum Start Pulse WidthMinimum ALE Pulse WidthMinimum Address Set-Up TimeMinimum Address Hold TimeAnalog MUX Delay TimeConditions(Figure 5)(Figure 5)(Figure 5)(Figure 5)RS=0 (Figure 5)MInTyp10010025251Max20020050502.5Unitsnsns

20、nsnsµsFrom ALEtH1, tH0t1H, t0HOE Control to Q Logic StateOE Control to Hi-ZCL=50 pF, RL=10k (Figure 8)CL=10 pF, RL=10k (Figure 8)125125250250nsnstcfctEOCConversion TimeClock FrequencyEOC Delay Timefc=640 kHz, (Figure 5) (Note 7)(Figure 5)9010010064011612808+2 µSµskHzClockPeriodsCINCOU

21、TInput CapacitanceTRI-STATE OutputAt Control InputsAt TRI-STATE Outputs10101515pFpFCapacitanceNote 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operatingthe device beyond its specified operating conditi

22、ons.Note 2: All voltages are measured with respect to GND, unless othewise specified.Note 3: A zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC.Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages on

23、e diode drop below ground or one diode drop greaterthan the VCCn supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by morethan 100 mV, the output code will be correct. To achieve an absolute 0VDC to 5VDC input vo

24、ltage range will therefore require a minimum supply voltage of 4.900 VDCover temperature variations, initial tolerance and loading.Note 5: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. See Figure 3. None of these A/Ds requires a zero or full-scale adjust. How

25、-ever, if an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltagescan be adjusted to achieve this. See Figure 13.Note 6: Comparator input current is a bias current into or out of the chopper s

26、tabilized comparator. The bias current varies directly with clock frequency and has littletemperature dependence (Figure 6). See paragraph 4.0.Note 7: The outputs of the data register are updated one clock cycle before the rising edge of EOC.Note 8: Human body model, 100 pF discharged through a 1.5

27、k resistor.4Functional DescriptionMultiplexer. The device contains an 8-channel single-endedanalog signal multiplexer. A particular input channel is se-lected by using the address decoder. Table 1 shows the inputstates for the address lines to select any channel. The ad-dress is latched into the dec

28、oder on the low-to-high transitionof the address latch enable signal.TABLE 1.The bottom resistor and the top resistor of the ladder net-work in Figure 1 are not the same value as the remainder ofthe network. The difference in these resistors causes theoutput characteristic to be symmetrical with the

29、 zero andfull-scale points of the transfer curve. The first output transi-tion occurs when the analog signal has reached +12 LSBand succeeding output transitions occur every 1 LSB later upto full-scale.The successive approximation register (SAR) performs 8 it-erations to approximate the input voltag

30、e. For any SAR typeSELECTEDADDRESS LINEconverter, n-iterations are required for an n-bit converter.Figure 2 shows a typical example of a 3-bit converter. In theANALOGCBAADC0808, ADC0809, the approximation technique is ex-CHANNELtended to 8 bits using the 256R network.IN0IN1IN2IN3IN4IN5IN6IN7LLLLHHHH

31、LLHHLLHHLHLHLHLHThe A/D converters successive approximation register(SAR) is reset on the positive edge of the start conversion(SC) pulse. The conversion is begun on the falling edge ofthe start conversion pulse. A conversion in process will be in-terrupted by receipt of a new start conversion pulse

32、. Con-tinuous conversion may be accomplished by tying theend-of-conversion (EOC) output to the SC input. If used inthis mode, an external start conversion pulse should be ap-plied after power up. End-of-conversion will go low between0 and 8 clock pulses after the rising edge of start conversion.The

33、most important section of the A/D converter is the com-CONVERTER CHARACTERISTICSThe ConverterThe heart of this single chip data acquisition system is its8-bit analog-to-digital converter. The converter is designed togive fast, accurate, and repeatable conversions over a widerange of temperatures. Th

34、e converter is partitioned into 3major sections: the 256R ladder network, the successive ap-proximation register, and the comparator. The convertersdigital outputs are positive true.The 256R ladder network approach (Figure 1) was chosenover the conventional R/2R ladder because of its inherentmonoton

35、icity, which guarantees no missing digital codes.Monotonicity is particularly important in closed loop feedbackcontrol systems. A non-monotonic relationship can cause os-cillations that will be catastrophic for the system. Additionally,the 256R network does not cause load variations on the ref-erenc

36、e voltage.5parator. It is this section which is responsible for the ultimateaccuracy of the entire converter. It is also the comparatordrift which has the greatest influence on the repeatability ofthe device. A chopper-stabilized comparator provides themost effective method of satisfying all the con

37、verter require-ments.The chopper-stabilized comparator converts the DC inputsignal into an AC signal. This signal is then fed through ahigh gain AC amplifier and has the DC level restored. Thistechnique limits the drift component of the amplifier since thedrift is a DC component which is not passed

38、by the AC am-plifier. This makes the entire A/D converter extremely insen-sitive to temperature, long term drift and input offset errors.Figure 4 shows a typical error curve for the ADC0808 asmeasured using the procedures outlined in AN-179.Functional Description(Continued)FIGURE 1. Resistor Ladder

39、and Switch TreeDS005672-13DS005672-2DS005672-14FIGURE 2. 3-Bit A/D Transfer CurveFIGURE 3. 3-Bit A/D Absolute Accuracy CurveDS005672-15FIGURE 4. Typical Error Curve6Timing DiagramDS005672-4FIGURE 5.7Typical Performance CharacteristicsDS005672-16FIGURE 6. Comparator IIN vs VIN(VCC=VREF=5V)DS005672-17

40、FIGURE 7. Multiplexer RON vs VIN(VCC=VREF=5V)TRI-STATE Test Circuits and Timing Diagramst1H, tH1t0H, tH0DS005672-18DS005672-21t1H, CL = 10 pFt0H, CL = 10 pFFIGURE 8.DS005672-19DS005672-22tH1, CL = 50 pFDS005672-20tH0, CL = 50 pFDS005672-23Applications InformationOPERATION1.0 RATIOMETRIC CONVERSIONTh

41、e ADC0808, ADC0809 is designed as a complete DataAcquisition System (DAS) for ratiometric conversion sys-tems. In ratiometric systems, the physical variable beingmeasured is expressed as a percentage of full-scale which isnot necessarily related to an absolute standard. The voltageinput to the ADC08

42、08 is expressed by the equation(1)VIN=Input voltage into the ADC0808Vfs=Full-scale voltageVZ=Zero voltage8DX=Data point being measuredDMAX=Maximum data limitDMIN=Minimum data limitA good example of a ratiometric transducer is a potentiom-eter used as a position sensor. The position of the wiper is d

43、i-rectly proportional to the output voltage which is a ratio of thefull-scale voltage across it. Since the data is represented asa proportion of full-scale, reference requirements are greatlyreduced, eliminating a large source of error and cost formany applications. A major advantage of the ADC0808,

44、ADC0809 is that the input voltage range is equal to the sup-ply range so the transducers can be connected directlyacross the supply and their outputs connected directly intothe multiplexer inputs, (Figure 9).Ratiometric transducers such as potentiometers, straingauges, thermistor bridges, pressure t

45、ransducers, etc., aresuitable for measuring proportional relationships; however,many types of measurements must be referred to an abso-lute standard such as voltage or current. This means a sys-Applications Information(Continued)The top of the ladder, Ref(+), should not be more positivethan the supp

46、ly, and the bottom of the ladder, Ref(), shouldtem reference must be used which relates the full-scale volt-age to the standard volt. For example, if VCC=VREF=5.12V,then the full-scale range is divided into 256 standard steps.The smallest standard step is 1 LSB which is then 20 mV.2.0 RESISTOR LADDE

47、R LIMITATIONSThe voltages from the resistor ladder are compared to theselected into 8 times in a conversion. These voltages arecoupled to the comparator via an analog switch tree which isreferenced to the supply. The voltages at the top, center andbottom of the ladder must be controlled to maintain

48、propernot be more negative than ground. The center of the laddervoltage must also be near the center of the supply becausethe analog switch tree changes from N-channel switches toP-channel switches. These limitations are automatically sat-isfied in ratiometric systems and can be easily met in groundreferenced systems.Figure 10 shows a ground referenced system with a sepa-rate supply and reference. In this system, the supply must betrimmed to match the reference voltage. For instance, if a5.12V is used, the supply should be a