大规模数字集成电路设计第二章VHDL语言程序的基本结构ppt课件

1、大规模数字集成电路设计大规模数字集成电路设计第二章第二章VHDLVHDL言语程序的根本构造言语程序的根本构造本章要点本章要点 VHDLVHDL程序的宏观构造；程序的宏观构造； 实体的根本格式及其在实体的根本格式及其在VHDLVHDL硬件设计硬件设计中的运用中的运用 构造体的根本格式及其在构造体的根本格式及其在VHDLVHDL硬件设硬件设计中的根本功能计中的根本功能 库的实意图义及运用方法。库的实意图义及运用方法。 2.1 VHDL程序组成部分及其功能程序组成部分及其功能VHDLVHDL程序程序实体实体EntityEntity构造体构造体ArchitectureArchitecture配置配置C

2、onfigurationConfiguration包集合包集合PackagePackage库库LibraryLibrary设计共享部分设计共享部分需编写的部分需编写的部分VHDL描画的总体构造描画的总体构造2.1 VHDL程序组成部分及其功能程序组成部分及其功能VHDLVHDL程序程序实体实体EntityEntity构造体构造体ArchitectureArchitecture配置配置ConfigurationConfiguration包集合包集合PackagePackage库库LibraryLibrary根本设计单元根本设计单元所必需的部分所必需的部分实体实体-规定设计单元的输入规定设计单元的

3、输入输出接口信号和引脚输出接口信号和引脚构造体构造体-定义设计单元的详细定义设计单元的详细构造或功能行为构造或功能行为 2.2 2.2 实体实体实体阐明的构造实体阐明的构造ENTITY ENTITY 实体名实体名 ISIS【类属参数阐明】；【类属参数阐明】；【端口阐明】；【端口阐明】；END END 实体名；实体名；2.2 2.2 实体阐明实体阐明 端口阐明端口阐明1 1端口名端口名2 2端口方向端口方向3 3数据类型数据类型2.2 2.2 实体阐明实体阐明 端口阐明端口阐明 端口阐明是对设计实体与外部接口的描画。端口阐明是对设计实体与外部接口的描画。包括对引脚信号称号、引脚信号的数据类包括对

4、引脚信号称号、引脚信号的数据类型、以及信号的输入、输出方向的描画。型、以及信号的输入、输出方向的描画。PORTPORT端口名：端口名： ； 端口名：方向端口名：方向 数据类型；数据类型；方向方向数据类型数据类型2.3 2.3 构造体构造体 构造体的构造ARCHITECTURE 构造体名 OF 实体名 IS【定义语句】内部信号、常数、数据类型等的定义；BEGIN【并行处置语句】；END 构造体名；2.3 2.3 构造体构造体 1构造体的命名 2定义语句 3并行处置语句2.3 2.3 构造体构造体 一个完好的构造体由两个根本层次组成：一个完好的构造体由两个根本层次组成：2) 2) 描画实体逻辑行为

5、的，以各种不同的描描画实体逻辑行为的，以各种不同的描述风格表示的功述风格表示的功能描画语句。能描画语句。1 1对数据类型，常数，信号，子程序和元对数据类型，常数，信号，子程序和元件等元素的阐件等元素的阐明部分。明部分。【例【例1 1】 二选一选择器二选一选择器ANDNOTANDORD1SELD0Qtmp1tmp2MUX2ID0Entity mux2id0 isPort(d0,d1,sel : in bit;q : out bit);End mux2id0;Architecture struc of mux isBeginprocess(d0,d1,sel)variable tmp1,tmp2,

6、tmp3 : bit;begintmp1:=d0 AND sel;tmp2:=d1 AND(NOT sel);q=tmp1 OR tmp2;end process;End struc;【例【例1 1】 二选一选择器二选一选择器【例【例 1-21-2】 二选一选择器的构造体阐明二选一选择器的构造体阐明( (续续) ) ARCHITECTURE connect OF mux ISARCHITECTURE connect OF mux IS- - 构造体定义构造体定义BEGINBEGIN - - 构造体开场标志构造体开场标志 PROCESS (d0, d1, sel)PROCESS (d0, d1,

7、 sel) - - 进程进程 VARIABLE tmp1, tmp2, tmp3: BIT; VARIABLE tmp1, tmp2, tmp3: BIT; - - 变量的声明变量的声明 BEGINBEGIN- - 进程开场标志进程开场标志 tmp1 := d0 AND sel;tmp1 := d0 AND sel;- - 变量赋值语句变量赋值语句 tmp2 := d1 AND (NOT sel);tmp2 := d1 AND (NOT sel);- - 变量赋值语句变量赋值语句 q = tmp1 OR tmp2;q = tmp1 OR tmp2; - - 信号赋值语句信号赋值语句 END P

8、ROCESS;END PROCESS;- - 进程终了进程终了END connect;END connect;- - 构造体终了构造体终了【例【例 1-21-2】 二选一选择器的构造体阐明二选一选择器的构造体阐明( (续续) ) ARCHITECTURE connect OF mux ISARCHITECTURE connect OF mux IS- - 构造体定义构造体定义BEGINBEGIN - - 构造体开场标志构造体开场标志 PROCESS (d0, d1, sel)PROCESS (d0, d1, sel) - - 进程进程1 1。 END PROCESS;END PROCESS;-

9、 - 进程进程1 1终了终了 PROCESS (d0, d1, sel)PROCESS (d0, d1, sel) - - 进程进程2 2。 END PROCESS;END PROCESS;- - 进程进程2 2终了终了 。- - 其它并行语句构造其它并行语句构造 END connect;END connect;- - 构造体终了构造体终了 Used to make associations within modelsUsed to make associations within models Associate a Entity and Architecture Associate a E

10、ntity and Architecture Associate a component to an Entity- Associate a component to an Entity-ArchitectureArchitecture Widely used in Simulation environmentsWidely used in Simulation environments Provides a flexible and fast path to design Provides a flexible and fast path to design alternativesalte

11、rnatives Limited or no support in Synthesis environments Limited or no support in Synthesis environments CONFIGURATION OF CONFIGURATION OF ISIS FOR FOR END FOR;END FOR; END; (1076-1987 version)END; (1076-1987 version) END CONFIGURATION; (1076-1993 version)END CONFIGURATION; (1076-1993 version)2.4 2.

12、4 配置配置 ConfigurationConfigurationPutting it all togetherPutting it all together Packages are a convenient way of storing and using information throughout an entire model. Packages consist of: Package Declaration (Required) Type declarations Subprograms declarations Package Body (Optional) Subprogram

13、 definitions VHDL has two built-in Packages Standard TEXTIO2.4 2.4 包集合包集合PackagePackage2.5 库 Contains a package or a collection of packages. Resource Libraries Standard Package IEEE developed packages Altera Component packages Any library of design units that are referenced in a design. Working Libr

14、ary Library into which the unit is being compiled. 必需放在VHDL程序最前面; 在VHDL程序中，可以有多个库，库和库之间相互独立; All packages must be compiled Implicit Libraries Work STD Note: Items in these packages do not need to be referenced,they are implied. LIBRARY Clause Defines the library name that can be referenced. Is a sym

15、bolic name to path/directory. Defined by the Compiler Tool. USE Clause Specifies the package and object in the library that you have specified in the Library clause.2.5 库LIBRARY STDLIBRARY STDn Contains the following packages:nstandard ( Types: Bit, Boolean, Integer, Real, and Time. All operator fun

16、ctions to support types)ntextio (File operations)n An implicit library (built-in)nDoes not need to be referenced in VHDL designTypes defined in Types defined in Standard PackageStandard Packagen Type BITn 2 logic value system (0, 1)nsignal a_temp : bit;n BIT_VECTOR array of bitsnsignal temp : bit_ve

17、ctor(3 downto 0);nsignal temp : bit_vector(0 to 3) ;n Type BOOLEANn (false, true)n Integern Positive and negative values in decimalnsignal int_tmp : integer; - 32 bit numbernsignal int_tmp1 : integer range 0 to 255; -8 bit numbernNote: Standard package has other types2.4.1 库的种类1 IEEE库std_logic_1164

18、(std_logic types & related functions) std_logic_arith (arithmetic functions) std_logic_signed (signed arithmetic functions) std_logic_unsigned (unsigned arithmetic functions)2 STD库 standard ( Types: Bit, Boolean, Integer, Real, and Time.All operator functions to support types) textio (File opera

19、tions)LIBRARY IEEELIBRARY IEEEContains the following packages: std_logic_1164 (std_logic types & related functions) std_logic_arith (arithmetic functions) std_logic_signed (signed arithmetic functions) std_logic_unsigned (unsigned arithmetic functions)Types defined in Types defined in std_logic_

20、1164 Packagestd_logic_1164 Package Type STD_LOGIC Type STD_LOGIC 9 logic value system ( 9 logic value system (UU, , X X, , 0 0, , 1 1, , Z Z, , WW, , L L, , HH, , - -) ) WW, , L L, , HH weak values (Not supported by weak values (Not supported by Synthesis)Synthesis) X X - used for unknown - used for

21、 unknown Z Z - (not - (not z z) used for tri-state) used for tri-state - - Don Dont Caret Care Resolved type: supports, signals with multiple drives. Resolved type: supports, signals with multiple drives. Type STD_ULOGIC Type STD_ULOGIC Same 9 value system as STD_LOGIC Same 9 value system as STD_LOGIC Unresolved type: Does not support multiple signal Unresolved type: Does not support multiple signal drives.Error will occur.drives.Error will occur.2.4.1 库的运用1 库的声明LIBRARY