九十一学年度国立高雄应用科技大学IC设计研习班

1、1. Verilog HDL Introduction (1)Two HDLs (Hardware Description Language) under IEEE Standards Verilog HDL: IEEE 1364, VHDL (Very High Speed I.C. HDL): IEEE 1164九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.11. Verilog HDL Introduction (2)Types of Descriptions: Structural Descriptions describes the connection o

2、f a circuit, i.e. net-list. Behavioral Descriptions describes the function of a circuit including always block, initial block, function, task. Data Flow Descriptions (or Register Transfer Level RTL Description) - describes the function using assignment, 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.11. Verilo

3、g HDL Introduction (2-1) Any type of descriptions can be mixed in a module such as the following figure.module name(port1,port2,);Input, output and variable declarationsalways block1Structural descritionAssign statementalways block2endmodule九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.11. Verilog HDL Introdu

4、ction (3) Behavioral Descriptionmodule D_FF(q, d, clk, reset);output q; input d, clk, reset;reg q;always (posedge reset or negedge clk)if (reset) q=1b0; else q=d;endmodule九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.11.Verilog HDL Introduction (4) An Example of Structural Descriptioninclude “D_FF.v”module T_

5、FF (q, clk, reset);output q;wire q, d;input clk, reset; D_FF dff0(q, d, clk, reset); not n1(d, q);endmoduledqqresetclkclkresetInstantiation實體化實體化九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1d1.Verilog HDL Introduction(4) What is the structural description of the following circuit ?abcdefgmodule dummy(a,b,c,

6、d,g);input a,b,c,d;output g;wire e,f;and u1(e, a, b);and u2(f, c, d);or u3(g, e, f);endmodule九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.11.Verilog HDL Introduction (5) What is the structural description of the following circuit: Ripple Carry Counter ? q clkreset q clkreset q clkreset q clkresetclockresetq0

7、q1q2q3九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.11.Verilog HDL Introduction (6)include “T_FF.v”module ripple_carry_counter(q, clock, reset);output 3:0 q;wire 3:0 q;input clock, reset;T_FF tff0 (q0, clock, reset);T_FF tff1 (q1, q0, reset);T_FF tff2 (q2, q1, reset);T_FF tff3 (q3, q2, reset);endmodule九十一學年度國

8、立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.11.Verilog HDL Introduction (7) Test Benchinclude “ripple_carry_counter.v”module stimulus;reg clk, reset;wire 3:0 q;ripple_carry_counter r1(q,clk,reset );initial clk=1b0;always#5 clk=clk;initialbegin reset=1b1; #15 reset=1b0; #180 reset=1b1; #10 reset=1b0; #20 $finish;en

9、dinitial$monitor($time,”output q= %d”, q);endmodule九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.11.Verilog HDL Introduction (7-1)include “ripple_carry_counter.v”module stimulus;reg clk, reset;wire 3:0 q;integer handle, desc;ripple_carry_counter r1(q,clk,reset );initial clk=1b0;always#5 clk=clk;initialbegin r

10、eset=1b1; #15 reset=1b0; #180 reset=1b1;#10 reset=1b0;#20 $finish; $fclose(handle);endinitialbegin handle=$fopen(“rcc.out”); desc=handle | 1; $fmonitor(desc, $time,”output q= %d”, q);endendmodule九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.11.Verilog HDL Introduction (8) The results after running test bench0

11、 output q= 020 output q= 130 output q= 240 output q= 350 output q= 460 output q= 570 output q= 680 output q= 790 output q= 8100 output q= 9110 output q= 10120 output q= 11130 output q= 12140 output q= 13 150 output q= 14160 output q= 15170 output q= 0180 output q= 1190 output q= 2195 output q= 0210

12、output q= 1220 output q=2九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.11.Verilog HDL Introduction (9) Wave formclockresetTime 0 5 10 15 20 25 190.195210 220 225Counter 0 1 2 3 4 2 .0 1 2九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.11.Verilog HDL Introduction (10) Data Flow Descriptions (Continuous Assignment)Example:

13、 assign sum=abcin;/ always (a or b or cin)/ sum=abcin; assign cout=(a&b) | (a&cin) | (b&cin);Where &: and, |:or, :xor. sum and cout should be wire type variables.九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.11.Verilog HDL Introduction(11) First ProjectDesign a Verilog description and testbench for a 4-bit ad

14、der .Hint: Hierarchical levelFull Adder4-bit Adder九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.11.Verilog HDL Introduction(12) Full Adder Modulemodule fadder(a, b, cin, sum, cout);input a, b, cin;output sum, cout;assign sum = a b cin;assign cout = (a &b) | (a&cin) | (b & cin);endmodule 4-bit adder ? Test Ben

15、ch ?九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.11.Verilog HDL Introduction(12-1)include “fadder.v”module adder4 (a, b, cin, sum, cout);input 3:0 a, b;input cin;output 3:0 sum;output cout; wire 2:0 c;fadder fa0(a0, b0, cin, sum0, c0); fadder fa1(a1, b1, c0, sum1, c1); fadder fa2(a2, b2, c1, sum2, c2); fadde

16、r fa3(a3, b3, c2, sum3, cout); endmodule九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1assign cout, sum=a+b+cin;fa3fa2fa1fa0a3a2a1a0b3b2b1b0c0c1c2cincoutsum0sum1sum2sum31.Verilog HDL Introduction(12-2)include “adder4.v”module st_adder4;reg cin; wire 3:0 sum;reg 3:0 a, b;reg 4:0 i,j;/integer i, j; wire cout;ad

17、der4 u1 (a, b, cin, sum, cout);initial begin cin=0; repeat(2) begin九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1 for (i=0; i=5d15; i=i+1) begin a=i; for(j=i; j=5d15;j=j+1) begin b=j; #5 $display ($time, “a=%d, b=%d, cin=%b, sum=%d, cout=%b”, a, b, cin, sum, cout); end end cin=cin;end /repeat$finish;end /ini

18、tialendmodulesel=0;repeat (2)beginsel=sel;end1.Verilog HDL Introduction(12-3)include “adder4.v”module st_adder4;reg cin; wire 3:0 sum;wire cout;reg 3:0 a, b;integer i, j, handle, desc;adder4 u1 (a, b, cin, sum, cout);initial Begin handle=$fopen(“adder4.out”); desc=handle |1; cin=0; repeat(2) begin f

19、or (i=0; i=d15; i=i+1) begin a=i; for(j=i; j (greater), =(greater or equal to), = (smaller than or equal to). Equality: = (equal to), != (not equal), =(equal on event), !=(not equal on event), 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.14. Data Processing (5) Operators (cont.) Bit-wised Operators: compleme

20、nt & Bit-wised and | Bit-wised or Bit-wised xor or Bit-wised xnorExamples:A= 1011B= 1101C=B /C=0010C=A&B; /C=1001C=A|B; /C=1111C=AB;/C=0110C=AB;/C=1001九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1逐位元運算module bitwise_operators (sel, a, b, c, cbout);input 2:0 sel;input 3:0 a, b;output 3:0 c;output cbout;reg 3

21、:0 c;reg cbout;always (sel or a or b)case (sel)3b001: c=b;3b010: c=a&b;.xxxx: cbout, c=a+b;yyyy: cbout, c=a-b;.default: ;endcaseendmoduleinclude “c:/xilinx/ylj/bitwised_op/bitwised_op.v”module test_bitwised_op;reg 4:0 i, j;reg 2:0 k, sel1;reg 3:0 a1, b1;wire 3:0 c1;bitwise_operators uut (.sel(sel1),

22、 .a(a1), .b(b1), .c(c1);initial for (i=0; i=5d15; i=i+1) begin a1=i; for (j=i; j=5d15; j=j+1) begin b1=j; for (k=1; k shift right 4; /B=011010, A=000001 E= Da=0011(+3)=a=0001= a=0000= a=0000= b=1000 (-8) =b=0100(+4) =b=1100(-4)=b=1110(-2)= b=1111(-1)= b=1111(-1) 符號擴充 (Sign Extension)算術左移a=0001 =a=00

23、10=a=0100=a=1000 (overflow)b=1110(-2) = b=1100(-4)= b=1000 (-8) =b=0000 (overflow)underflowunderflowmodule arith_shift (sel, A, B, num, V);input sel; 3d2:temp, B=A4, A2;input 4:0 A; 3d3:temp, B=A4, A3;input 2:0 num; 3d4:temp, B=A4, A4;output 4:0 B; 3d5:temp, B=A4, A5;output V; default: ;reg 4:0 B; e

24、ndcasereg V; elsereg temp; beginalways(sel or A or num) temp=A4;if (sel) case (num)case (num) 3d1: B=A1; . default: ; endcase V=temp B4; end endmoduleinclude “arith_shift.v”module st_arith_shift;wire 4:0 b;wire v;reg 4:0 a;reg 2:0 num;reg 5:0 i;reg 2:0 j;reg sel;arith_shift u1 (sel, a, b, num, v);in

25、itial begin sel=0; repeat(2) begin for (i=0; i=5d31; i=i+1) begin a=i; for (j=0; j1;2b01:Outp=Outp1;2b10: begin aout,Outp= aout,Outp1; OutpLength-1=aout; enddefault: ;endcaseendendmodule 101001 01001 0101 Test Benchinclude “shifter.v”module stimulus_shifter;reg clk, reset,Load;reg 1:0 func;reg 3:0 I

26、np;wire 3:0 Outp;shifter r1(Inp,clk,reset,Outp,Load, func);initial clk=1b0;always #5 clk=clk;initialbegin reset=1b1;Load=1b0; #10 reset=1b0; Inp=4b0110; #10 Load=1b1; #10 Load=1b0;func=2b00; #10 func=2b10; #10 func=2b01; #10 func=2b11; #10 $finish;endinitial$monitor($time,”output Outp= %b”, Outp);en

27、dmodule4. Data Processing (9) Operators (cont.) Conditional expression assign out=control ? In1: In0; / 2x1 multiplexer/ always (In1 or In0 or control) / if (control) out=In1; else out=In0; assign out=C1? (C0? in3:in2):(C0?in1:in0); / 4x1 multiplexer九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.15. Behavioral

28、 Modeling (1)Types of Behavioral descriptions: initial blocks always blocks Functions Tasks九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.15. Behavioral Modeling (2) Statements in behavioral description Procedural assignment: Blocking assignment Non-blocking assignment九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.15. Be

29、havioral Modeling (3) Blocking assignmentExample: always (posedge clk or negedge reset or .) if (reset) . else if (.) . else begin a=b+c; / if b=3, c=2, then a=5 k=a+2; / k=5+2 =7 end sequentially executed九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.15. Behavioral Modeling (4) Non-blocking assignmentExample:

30、 always (posedge clk or posedge reset or .) if (reset) . else if (.) . else begin a=b+c; / if a=2, b=3, c=2, then new value of a=5 k=a+2; / k=2+2 =4, the assignment use old value of a k=.; /illegal assignment end parallelly executed九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.15. Behavioral Modeling (5) Note

31、s on Blocking and Non-blocking Assignment For any process (always block, function or task), mixed usage of Blocking and Non-blocking assignment is inhibited !Example: always . begin a=. ; . a =.; endinhibited九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.15. Behavioral Modeling (6): More Examples on Non_blocki

32、ng AssignmentA One Bit Piplined Adder:A3A2A1A0B3B2B1B0S0S1S2S3a bcout cin sumcoutmodule pipefa(a, b, sum, clk, reset);input a, b, clk, reset;output sum;reg cout, sum;always (posedge clk or posedge reset)If (reset)begin sum=0; cout=0; endelsebegin sum=abcout; cout=(a&b)|(a&cout)|(b&cout);endendmodule

33、九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1clkreset5. Behavioral Modeling (7): A 4-Bit Piplined Addera bcout cin sumc1A03A02A01A00B03B02B01B00S00S01S02S03a bcout cin sumc2A13A12A11A10B13B12B11B10S10S11S12S13a bcout cin sumc3A23A22A21A20B23B22B21B20S20S21S22S23a bcout cin sumcoutA33A32A31A30B33B32B31B30S30

34、S31S32S3340*1000=4000040+10*999=100305. Behavioral Modeling (8): A 4-Bit Piplined Addermodule pipe4adder(a, b, cin, sum, cout, clk, reset);input 3:0 a, b; input clk, reset, cin;output 3:0 sum; output cout;reg 3:1 c;reg3:0sum;reg cout;always (posedge reset or posedge clk)if (reset)begin sum0=1b0; sum

35、1=1b0; sum2=1b0; sum3=1b0; cout=1b0; c1=1b0; c2=1b0; c3=1b0; end else九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1begin sum0= a0b0cin; sum1= a1b1c1; sum2= a2b2c2; sum3= a3b3c3; c1=(a0&b0) | (a0&cin) | (b0&cin); c2=(a1&b1) | (a1&c1) | (b1&c1); c3=(a2&b2) | (a2&c2) | (b2&c2); cout=(a3&b3) | (a3&c3 )| (b3&c3);

36、endendmoduleinclude “pipeadder4.v”module st_pipeadder4;reg cin,clk,reset, flag; wire 3:0 sum;reg 3:0 a, b, y0,y1,y2,y3, z3, z2.z1,z0,y,z;Reg 1:0 k;integer i, j, handle, desc;pipeadder4 u1 (y, z, cin, sum, cout, clk, reset);always #5 clk=clk;always (posedge clk or posedge reset)if (reset)begin y0=0;y

37、1=0; y2=0; y3=0;k=0; cin=0;z0=0;z1=0; z2=0; z3=0;y=0;z=0; endelsebegincase (k) 2b00: begin y0=a; z0=b; y=y13, y22, y31, y00; z=z13, z22, z31, z00; end 2b01: begin y1=a; z1=b; y=y23, y32, y01, y10; z=z23, z32, z01, z10; end 2b10:begin y2=a;z2=b; y=y33, y02, y11, y20; z=z33, z02, z11, z20; end 2b11: b

38、egin y3=a; z3=b; y=y03, y12, y21, y30; z=z03, z12, z21, z30; enddefault:;endcase$fdisplay(desc, $time, “y=%b, z=%b, cin=%b, sum=%b, cout=%b”,y,z,cin,sum,cout);if (flag=1b1 & k=2b11)begin $finish; $fclose(handle); endelse k=k+1;end for (i=0; i=d15; i=i+1) begin a=i; for(j=i; j=d15;j=j+1) #10 b=j;end

39、cin=cin;end /repeatflag=1b1;end /initialinitial Beginclk=0; reset=1b1; #5 reset=1b0; handle=$fopen(“pipeadder4.out”); desc=handle |1; cin=0; flag=1b0; repeat(2) begin5. Behavioral Modeling (8-1): A 4-Bit Piplined Adder V2module pipe4adderv2(a, b, cin, sum, cout, clk, reset);input 3:0 a, b;Reg a1.b1,

40、a21,a22,b21,b22, sum00, sum01, sum02, sum10, sum11, sum20, a31, b31, a32, a33, b32, b33; input clk, reset, cin;output 3:0 sum; output cout;reg 3:1 c; reg3:0 sum; reg cout;always (posedge reset or posedge clk)if (reset)begin sum0=0; sum1=0; sum2=0; sum3=0; cout=0; c1=0; c2=0; c3=0; end ElseBegin a1=a

41、1; b1=b1;a21=a2; b21=b2;a22=a21; b22=b21;a31=a3; b31=b3;a32=a31; b32=b31;a33=a32; b33=b32;九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1 sum00= a0b0cin; sum01= sum00; sum02= sum01; sum0=sum02; sum10= a1b1c1; sum11= sum10; sum1= sum11; sum20= a22b22c2; sum2=sum20; sum3= a33b33c3; c1=(a0&b0) | (a0&cin) | (b0&c

42、in); c2=(a1&b1) | (a1&c1) | (b1&c1); c3=(a22&b22) | (a22&c2) | (b22&c2); cout=(a33&b33) | (a33&c3 )| (b33&c3);endendmoduleinclude “pipeadder4.v”module st_pipeadder4;reg cin,clk,reset, flag; wire 3:0 sum;reg 3:0 a, b;reg 3:0 counter;integer i, j, handle, desc;pipeadder4 u1 (a, b, cin, sum, cout, clk,

43、 reset);always #5 clk=clk;always (posedge clk or posedge reset)if (reset)begin counter=4; endelseBegin if (counter!=0) begin counter=counter-1; fdisplay(desc,”a=%b,b=%b”, a,b); endelse $fdisplay(desc, $time, “a=%b, b=%b, cin=%b, sum=%b, cout=%b”,a,b,cin,sum,cout);if (flag=1b1) begin $finish; $fclose

44、(handle); endend for (i=0; i=d15; i=i+1) begin a=i; for(j=i; j=d15;j=j+1) #10 b=j;end cin=cin;end /repeatflag=1b1;end /initialinitial Beginclk=0; reset=1b1; #5 reset=1b0; handle=$fopen(“pipeadder4.out”); desc=handle |1; cin=0; flag=1b0; repeat(2) begin5. Behavioral Modeling (9) Race Condition for Bl

45、ocking Assignmentalways (posedge clock) a=b;always (posedge clock) b=a; Solution:always (posedge clock) a=b;always (posedge clock) b=a;九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.15. Behavioral Modeling (10) Statements in Behavioral Modeling if statement for statement case statement while statement repeat s

46、tatement forever statement fork-jointFor synthesis and simFor sim only九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.15. Behavioral Modeling (11) if statement for statementExample: 8x3 Priority Encoder always (in) for (I=0; I=0; I=I-1) if (inI=1b1) out=I;In7 has the highest priorityIn0 has the highest priority

47、九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1module Gpencoder(in, out); parameter leng=3; input 2*leng-1:0 in; output leng-1:0 out; reg leng-1:0 out; reg leng:0 I; always (in) for (I=0; I= 2*leng-1; I=I+1) if (inI=1b1) out=I;endmodule5. Behavioral Modeling (12)case statementExample: 4X1 multiplexermodule Mu

48、x4 (s1, s0, i0, i1 , i2, i3, out);input s1, s0, i0, i1 , i2, i3;output out;reg out;always (s1 or s0 or i0 or i1 or i2 or i3)case (s1,s0)2b00: out=i0;2b01: out=i1;2b10: out=i2;2b11: out=i3;default: ;endcaseendmodule九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1s1 s05. Behavioral Modeling (13) Two Variations o

49、f case Statement - casex and casezcasex: x and z are taken as dont carecasez: all zs are taken as dont careExample: 4x2 priority encoder casex (encoding) 4b1xxx: out=2d3; 4b01xx: out=2d2; 4b001x: out=2d1; 4b0001: out=2d0; default:;endcase九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1casez (encoding) 4b1zzz:

50、out=3; 4b01zz: out=2; 4b001z: out=1; 4b0001: out=0; default:;endcase5. Behavioral Modeling (13-1)Projects: Design the following combinational circuit with parameters.(1) Decoder(2) Priority Encoder(3) Multiplexer(4) De-multiplexer5. Behavioral Modeling (13-2)module Generic_Decoder(inp, outp); parame

51、ter inp_leng=3; parameter outp_leng=8; input inp_leng-1:0 inp; output outp_leng-1:0 outp; reg outp_leng-1:0 outp; always (inp) outp= 1=0; I=I+1) if (inpI=1b1) outp= I;endmodule5. Behavioral Modeling (13-4)module Generic_Mux(inp, sel, outp); parameter inp_leng=8; parameter sel_leng=3; input inp_leng-

52、1:0 inp; input sel_leng-1:0 sel; output outp; reg outp; always (inp or sel) outp= inpsel;endmodule5. Behavioral Modeling (13-5)module Generic_DeMux(inp, sel, outp); parameter outp_leng=8; parameter sel_leng=3; output outp_leng-1:0 outp; input sel_leng-1:0 sel; input inp; reg outp_leng-1:0 outp; alwa

53、ys (inp or sel) begin outp=0; outpsel= inp; endEndmoduleGeneric_DeMux #(16,4) ( .);5. Behavioral Modeling (14) Example: Traffic Light ControllerS0S1S2S3S4X=0X=1X=1X=0S0: Hwy=G Cntry=RS1: Hwy=Y Cntry=RS2: Hwy=R Cntry=RS3: Hwy=R Cntry=GS4: Hwy=R Cntry=Y九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.15. Behaviora

54、l Modeling (15)define TRUE 1b1define FALSE 1b0define RED 2d0define YELLOW 2d1define GREEN 2d2define S0 3d0define S1 3d1define S2 3d2define S3 3d3define S4 3d4define Y2RDELAY 3define R2GDELAY 2module sig_control (hwy,cntry,x,clock,clear);output 1:0 hwy, cntry;reg 1:0 hwy, cntry;input x, clock, clear;

55、reg 2:0 state;reg 1:0 count;always (posedge clear or posedge clock)if (clear)begin state=S0; hwy=GREEN; cntry=RED; count=0;endelse九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.15. Behavioral Modeling (16)begin case (state) S0: begin hwy=GREEN; cntry=RED; if (x=TRUE) begin state=S1; count=Y2RDELAY; end end S1:

56、 begin hwy=YELLOW; cntry=RED; count=count-1; if (count=0) begin state=S2; count=R2GDELAY; endendS2: begin hwy=RED; cntry=RED; count=count-1; if (count=0) state=S3; endS3: begin hwy=RED; cntry=GREEN; if (x=FALSE) begin state=S4; count=R2GDELAY; end endS4: begin hwy=RED; cntry=YELLOW; count=count-1; i

57、f (count=0) state=S0; enddefault:;endcaseendendmodule九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.15. Behavioral Modeling (17)Project 2: Complete a design with test bench for the following finite state machine: The cost of each copy of news paper is $15. The vending machine can accept only $10 and $5 coins.

58、Each transaction can be done only when 15 dollars or more are inserted. If more than 15 dollars inserted, no changes at all.九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.15. Behavioral Modeling (18) Function & Task Similar to subroutine in C language and procedure in Pascal language respectively Function has

59、only one output and some inputs Task has more than one output and input九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.15. Behavioral Modeling (19) A Task Example:module operation (a, b, ab_and, ab_or, ab_xor);input 15:0 a, b;output 15:0 ab_and, ab_or, ab_xor;task bit_wise_oper;output 15:0 aband, abor, abxor;in

60、put 15:0 aa, bb;begin aband= aa& bb; abor = aa | bb; abxor= aa bb;endendtaskalways (a or b) bit_wise_oper(ab_and, ab_or, ab_xor, a, b); endmodule九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.15. Behavioral Modeling (20) A function Example:define LEFT_SHIFT 1b0define RIGHT_SHIFT 1b1module shifter(LorR, addrin,