基于fpga的密码锁设计

1、library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fen_pin isport( clk:in std_logic; clk_1ms:out std_logic; clk_10ms:out std_logic);end fen_pin;architecture FF2 of fen_pin issignal Q0:std_logic_vector(16 downto 0);signal Q1:std_logic_vector(17 downto 0);signal c0:std_log

2、ic;signal c1:std_logic;beginprocess(clk) begin if clk'event and clk='1' then if Q0=50000 then -1ms Q0<="00000000000000000" c0<=not c0; else Q0<=Q0+1; end if; if Q1=250000 then c1<=not c1; -10ms Q1<="000000000000000000" else Q1<=Q1+1; end if; end if;

3、end process;clk_1ms<=c0;clk_10ms<=c1;end FF2;-FEN PINlibrary ieee;use ieee.std_logic_1164.all;entity an_jian isport(clk_10ms:in std_logic;-时钟 col:in std_logic_vector(3 downto 0);-列扫描输入 row:out std_logic_vector(3 downto 0);-行扫描输出 keyout:out std_logic_vector(3 downto 0);-编码输出end an_jian;architec

4、ture FF1 of an_jian issignal rowreg: std_logic_vector(3 downto 0);signal con : std_logic_vector(7 downto 0);beginprocess(clk_10ms) begin if clk_10ms'event and clk_10ms= '1' then case rowreg is when "0111" => rowreg<= "1011" when "1011" => rowreg<

5、= "1101" when "1101" => rowreg<= "1110" when "1110" => rowreg<= "0111" when others => rowreg<= "0111" end case; end if;end process;row <= rowreg; -输出行扫描信号con <= rowreg & col;-合并行列信号process(clk_10ms) begin if clk_

6、10ms'event and clk_10ms= '1' then case con is when "11100111" => keyout<= "0001"-1 when "11101011" => keyout<= "0010"-2 when "11101101" => keyout<= "0011"-3 when "11101110" => keyout<= "010

7、0" -4 when "11010111" => keyout<= "0101"-5 when "11011011" => keyout<= "0110"-6 when "11011101" => keyout<= "0111"-7 when "11011110" => keyout<= "1000"-8 when "10110111" => keyou

8、t<= "1001"-9 when "10111011" => keyout<= "0000"-0 when "10111101" => keyout<= "1010"-10 when "10111110" => keyout<= "1011" -11 when "01110111" => keyout<= "1100"-12 when others =>

9、keyout<="1111"end case; end if; end process;end FF1;-AN JIANlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity an_jian_chu_li2 isport( clk_1ms:in std_logic; keyin:in std_logic_vector(3 downto 0); clk_key:out std_logic);end an_jian_chu_li2;architecture FF3 of

10、 an_jian_chu_li2 is signal key_temp:std_logic_vector(3 downto 0);signal count:std_logic_vector(9 downto 0);signal qq:std_logic;begin process(clk_1ms,count,key_temp,keyin) begin if keyin/="1111" then if clk_1ms'event and clk_1ms='0' then if key_temp=keyin then if count<1000 t

11、hen count<=count+1; else key_temp<="1111" end if; else key_temp<=keyin; count<="0000000000" end if; end if; end if; end process;qq<='1' when count>15 and count <30 else '0'clk_key<=qq;end FF3;-AN JIAN CHU LIlibrary ieee;use ieee.std_logic_1

12、164.all;use ieee.std_logic_unsigned.all;entity bi_jiao isport(clk_key:in std_logic; keyin:in std_logic_vector(3 downto 0); led_r,led_b:out std_logic);end bi_jiao;architecture FF4 of bi_jiao issignal key_temp:std_logic_vector(3 downto 0);signal count:std_logic_vector(1 downto 0);signal mi:std_logic_v

13、ector(11 downto 0);signal reg:std_logic_vector(11 downto 0);begin process(clk_key,keyin) begin if keyin/="1111" then if clk_key'event and clk_key='1' then if keyin=12 then count<="00"mi<="000000000000" led_r<='1'led_b<='1' else if

14、 count=0 then mi(11 downto 8)<=keyin; count<=count+1; elsif count=1 then mi(7 downto 4)<=keyin; count<=count+1; elsif count=2 then mi(3 downto 0)<=keyin; count<=count+1;else null; if count=3 and keyin=10 then reg<=mi; led_r<='0'led_b<='0' elsif keyin=11 the

15、n if reg=mi then led_r<='0'led_b<='1' else led_r<='1'led_b<='0' if mi="001100010100" then -密码314 led_r<='0'led_b<='1' end if; end if;end if; end if;end if;end if;end if; end process;end FF4;-BI JIAOlibrary IEEE;use IEEE.std_

16、logic_1164.all;use IEEE.std_logic_unsigned.all; entity MMS isport( clk:in std_logic; col:in std_logic_vector(3 downto 0);-列扫描输入 row:out std_logic_vector(3 downto 0);-行扫描输出 led_b,led_r:out std_logic);end MMS;architecture one of MMS iscomponent fen_pinport( clk:in std_logic; clk_1ms:out std_logic; clk

17、_10ms:out std_logic);end component;component an_jian port(clk_10ms:in std_logic;-时钟 col:in std_logic_vector(3 downto 0);-列扫描输入 row:out std_logic_vector(3 downto 0);-行扫描输出 keyout:out std_logic_vector(3 downto 0);-编码输出end component;component an_jian_chu_li2port(clk_1ms:in std_logic; keyin:in std_logic_vector(3 downto 0); clk_key:out std_logic);end component;component bi_jiao port(clk_key:in std_logic; keyin:in std_logic_vector(3 downto 0); led_r,led_b:out std_logic);end component;signal a,b,d:std_logic;signal c,f:std_logic_vector(3 downto 0);beginG1:fen_pin port map(clk