病房呼叫系统报告

1、可编程逻辑器件应用项目报告书项目名称：病房呼叫系统指导老师：龚兰芳姓名：曾锦聪学号：080212216班级：08电子2班目录一、设计要求-二、设计方案-三、设计程序-四、管脚分配-五、硬件下载实现现象描述-六、体会与收获-一、设计要求1.用19个开关模拟9个病房的呼叫输入信号，1号优先级最高；19优先级依次降低；2.用一个数码管显示呼叫信号的号码；没信号时显示0；有多个信号呼叫时，显示优先级最高的呼叫号（其他呼叫用指示灯显示）；3.凡有呼叫发出5秒的呼叫声；4.对低优先级的呼叫进行存储，处理完高优先级的呼叫，再进行低优先级呼叫的处理（附加）。二、设计方案用层次化的设计，将功能分为三个部分，第一

2、部分输入模块，用来输入八个病房的房号。第二部分输出模块，用来显示八个病房的房号。第三部分显示模块，使优先级低的病房房号用彩灯显示出来。三、设计程序第一部分：抢答模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity jnb isport(clk,i:in std_logic; u,r,t,y:in std_logic; led3: out std_logic_vector(3 downto 0); k:out std_logic_

3、vector(2 downto 0); o:out std_logic_vector(3 downto 0);end;architecture one of jnb issignal n:integer range 0 to 1;signal clk_1k,clk_100h:std_logic;signal data:std_logic_vector(3 downto 0);signal s:std_logic_vector(6 downto 0);signal h:std_logic_vector(2 downto 0);signal j:std_logic_vector(3 downto

4、0);begin process (clk) variable cnt1:integer range 0 to 250; variable cnt2:integer range 0 to 100; begin if clk'event and clk='1' then if cnt1=250 then cnt1:=0; if cnt2=100 then cnt2:=0; clk_1k<=not clk_1k; else cnt2:=cnt2+1; end if; else cnt1:=cnt1+1; end if; end if; end process;proc

5、ess(clk_1k)begin if i='1' then if n=0 then if u='0'then led3<="0001" j<="0111" n<=n+1; elsif r='0' then led3<="0010" j<="1011" n<=n+1; elsif t='0' then led3<="0011" j<="1101" n<=n+1

6、; elsif y='0' then led3<="0100" j<="1110" n<=n+1; end if; end if; else h<="100" n<=0; led3<="0000" j<="1111" end if;k<=h;o<=j;end process;end;第二部分：数值输入模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_un

7、signed.all;use ieee.std_logic_arith.all;entity WER isport(rst,clk,tsr,en:in std_logic; p:out std_logic; c,d:in std_logic_vector(3 downto 0); duon:out std_logic_vector(5 downto 0); led3:in std_logic_vector(3 downto 0); cout:out std_logic_vector(6 downto 0);end;architecture one of WER issignal t,r:int

8、eger range 0 to 1;signal w:integer range 0 to 6;signal clk_1k:std_logic;signal clk_100h:std_logic;signal cnt6:integer range 0 to 3;signal data:std_logic_vector(3 downto 0);signal dout:std_logic_vector(5 downto 0);signal s:std_logic_vector(6 downto 0);signal led1,led2:std_logic_vector(3 downto 0);beg

9、in process (clk) variable cnt1:integer range 0 to 250; variable cnt2:integer range 0 to 100; begin if clk'event and clk='1' then if cnt1=250 then cnt1:=0; if cnt2=100 then cnt2:=0; clk_1k<=not clk_1k; else cnt2:=cnt2+1; end if; else cnt1:=cnt1+1; end if; end if; end process; process (

10、clk) variable cnt1:integer range 0 to 5000; variable cnt2:integer range 0 to 5000; begin if clk'event and clk='1' then if cnt1=5000 then cnt1:=0; if cnt2=5000 then cnt2:=0; clk_100h<=not clk_100h; else cnt2:=cnt2+1; end if; else cnt1:=cnt1+1; end if; end if; end process; process(clk_1

11、k) begin if clk_1k'event and clk_1k='1' then if cnt6=33 then cnt6<=0; else cnt6<=cnt6+1; end if; end if;end process;process(cnt6)begin case cnt6 is when 0=>dout<="111110" when 1=>dout<="111101" when 2=>dout<="111011" when others=>n

12、ull; end case;end process;process(dout)begin case dout is when"111110"=>data<=led1; when"111101"=>data<=led2; when"111011"=>data<=led3; when others=>null; end case;end process;process(clk_100h)beginif tsr='0' then led1<="0000" l

13、ed2<="0000" t<=0;else if rst='0' then t<=1; p<='0' led2<=c;led1<=d; elsif clk_100h'event and clk_100h='1' and t=1 then if en='1' then if (led1<="0000") then led1<="1001" led2<=led2-1; if (led2<="0000

14、") then led1<="0000" led2<="0000" if w<=5 then p<='1' w<=w+1; else p<='0' end if; else p<='0' end if; else led1<=led1-1; end if; else t<=t-1; end if; end if;end if;end process;process(data)begin case data is when"0000&q

15、uot;=>s<="0111111"-0 when"0001"=>s<="0000110"-1 when"0010"=>s<="1011011"-2 when"0011"=>s<="1001111"-3 when"0100"=>s<="1100110"-4 when"0101"=>s<="1101101"-

16、5 when"0110"=>s<="1111101"-6 when"0111"=>s<="0000111"-7 when"1000"=>s<="1111111"-8 when"1001"=>s<="1101111"-9 when others=>null; end case;end process;duon<=dout;cout<=s;end;第三部分：译码模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity yima isport( h:in std_logic_vector(6 downto 0); a,b,c,d,e,f,g:out std_logic);end;architecture one of yima isbegin g<=h(6);