基于Verilog的数字密码锁设计

1、精选文档课程设计报告课程设计题目：基于Verilog的数字密码锁设计 学 号：201520070209同学姓名：尹景兴专 业：通信工程班 级：1521301指导老师：钟凯 2018年 1月 12 日目 录一、课程设计内容- 1 -二、实现思路- 1 -1.解锁过程- 1 -2.报警过程- 1 -3.重置密码过程- 1 -三、实现程序- 2 -四、仿真验证- 5 -1.解锁过程- 5 -2.报警过程- 6 -3.重置密码过程- 8 -五、设计心得- 11 -一、 课程设计内容设计一个4位串行数字密码锁，要求如下：1. 开锁密码为4位二进制，当输入密码与锁内给定的密码全都时，方可开锁。否则进入“错

2、误”状态，发出报警信号。2. 锁内的密码可调。3. 串行数字密码锁的报警，直到按下复位开关，才停下。此时，数字密码锁又自动等待下一个开锁状态。二、 实现思路1. 解锁过程密码锁出厂之前预设一个初始密码，在本课程设计中将其预设为0101。在密码锁上锁状态下,输入正确密码，密码锁打开。2. 报警过程当输入的密码与锁内密码不全都时，蜂鸣器响起，直到按下取消按键，蜂鸣器才停止鸣叫。3. 重置密码过程重置密码时，需先验证原密码是否正确。当输入原密码正确，才可以输入新密码，设置新密码为锁内密码。三、 实现程序module coded_lock(clk,in,set,pause,value1,value2,

3、store,bee,status,temp_set,ook); input clk,in,set,pause; output reg bee = 0; output reg status = 0; output reg temp_set = 0; output reg ook = 0; output reg3:0 value1; output reg3:0 value2; output reg3:0 store; reg en = 1; reg2:0 i = 0; reg2:0 j = 0; reg2:0 k = 0; reg2:0 count1 = 0; reg2:0 count2 = 0;

4、 reg2:0 count3 = 0; reg3:0 keynum = 4'b0101; always (posedge clk) begin if(set = 1) fork temp_set <= 1; value1 <= 4'bxxxx; value2 <= 4'bxxxx; store <= 4'bxxxx; i <= 0; j <= 0; k <= 0; ook <= 0; count1 <= 0; count2 <= 0; count3 <= 0; join end always (p

5、osedge clk) begin if(temp_set = 0) begin case(en,in) 2'b11: begin value1i <= 1'b1; i <= i + 1; count1 <= count1 + 1;end 2'b10: begin value1i <= 1'b0; i <= i + 1; count1 <= count1 + 1;end endcase end end always (posedge clk) begin if(count1 = 4) begin if(value1 = key

6、num) status <= 1; else bee <= 1; i <= 0; count1 <= 0; value1 <= 4'bxxxx; end end always (posedge clk) begin if(pause = 1) bee <= 0; end always (posedge clk) begin if(temp_set = 1 && ook = 0) begin case(en,in) 2'b11: begin value2j <= 1'b1; j <= j + 1; count

7、2 <= count2 + 1;end 2'b10: begin value2j <= 1'b0; j <= j + 1; count2 <= count2 + 1;end endcase end end always (posedge clk) begin if(count2 = 4) begin if(value2 = keynum) ook <= 1; j <= 0; count2 <= 0; value2 <= 4'bxxxx; end end always (posedge clk) begin if(ook =

8、 1) begin case(en,in) 2'b11: begin storek <= 1'b1; k <= k + 1; count3 <= count3 + 1;end 2'b10: begin storek <= 1'b0; k <= k + 1; count3 <= count3 + 1;end endcase end end always (posedge clk) begin if(count3 = 4) begin keynum <= store; temp_set <= 0; ook <=

9、0; k <= 0; count3 <= 0; end end endmodule 四、 仿真验证1. 解锁过程测试平台代码：timescale 1ns/1nsmodule text; reg clk,set,pause; reg in; wire bee,status,ook; wire3:0 value1,value2; wire3:0 store; wire temp_set; coded_lock temp(.clk(clk),.in(in),.set(set),.pause(pause),.bee(bee),.ook(ook),.status(status),.value

10、1(value1),.value2(value2),.store(store),.temp_set(temp_set); always #10 clk = clk; initial fork clk = 0; in = 1'bx; set = 0; pause = 0; join initial begin #123 in = 1'b1; #23 in = 1'bx; #45 in = 1'b0; #23 in = 1'bx; #45 in = 1'b1; #23 in = 1'bx; #45 in = 1'b0; #23 in

11、= 1'bx; end endmodule 如图，当输入预设密码0101时，图中status由0变为1，表示密码锁打开。2. 报警过程测试平台代码：timescale 1ns/1nsmodule text3; reg clk,set,pause; reg in; wire bee,status,ook; wire3:0 value1,value2; wire3:0 store; wire temp_set; coded_lock temp3(.clk(clk),.in(in),.set(set),.pause(pause),.bee(bee),.ook(ook),.status(sta

12、tus),.value1(value1),.value2(value2),.store(store),.temp_set(temp_set); always #10 clk = clk; initial fork clk = 0; in = 1'bx; set = 0; pause = 0; join initial begin #123 in = 1'b1; #23 in = 1'bx; #45 in = 1'b1; #23 in = 1'bx; #45 in = 1'b0; #23 in = 1'bx; #45 in = 1'

13、b0; #23 in = 1'bx; #123 pause = 1; #23 pause = 0; end endmodule如下图，当输入密码0011时，与锁内密码不全都，bee由0变为1，表示蜂鸣器响起。当按下pause按钮时，bee由1变为0，表示蜂鸣器停止鸣叫。3. 重置密码过程测试平台代码：timescale 1ns/1nsmodule text2; reg clk,set,pause; reg in; wire bee,status,ook; wire3:0 value1,value2; wire3:0 store; wire temp_set; coded_lock te

14、mp2(.clk(clk),.in(in),.set(set),.pause(pause),.bee(bee),.ook(ook),.status(status),.value1(value1),.value2(value2),.store(store),.temp_set(temp_set); always #10 clk = clk; initial fork clk = 0; in = 1'bx; set = 0; pause = 0; join initial begin #123 set = 1; #21 set = 0; #123 in = 1'b1; #21 in

15、 = 1'bx; #45 in = 1'b0; #21 in = 1'bx; #45 in = 1'b1; #21 in = 1'bx; #45 in = 1'b0; #21 in = 1'bx; #125 in = 1'b0; #21 in = 1'bx; #45 in = 1'b1; #21 in = 1'bx; #45 in = 1'b0; #21 in = 1'bx; #45 in = 1'b1; #21 in = 1'bx; #125 in = 1'b0;

16、#21 in = 1'bx; #45 in = 1'b1; #21 in = 1'bx; #45 in = 1'b0; #21 in = 1'bx; #45 in = 1'b1; #21 in = 1'bx;end endmodule 如下图，当正确输入预设密码0101时，ook由0变为1，表示可以更改密码，更改密码为1010。接着，输入新密码1010，status由0变为1，表示密码锁被新密码打开，如下图。五、 设计心得通过这次课程设计，我更深化生疏了Verilog编程的各个过程和原理，并且，成功地做出了一个产品的简化模型极大地挺高了我的学习爱好。当然，设计过程中也遇到了各种问题和困难，我极力克服，过后感觉受益匪浅。我会再接再厉的。Bingo!东华理工高校课程设计评分表同学姓名：尹景兴 班级：1521301 学号：201520070209课程设计题目：基于Verilog的数字密码锁设计 项目内容满分实 评选题能结合所学课程学问、有肯定的力量训练。符合选题要求（5人一题）10工作量适中，难易度合理10能力水平能娴熟应用所学学问，有肯定查阅文