EDA中用VHDL语言编程的实验

1、EDA课程中VHDL的分频程序(1)将 32KHz分成1KHz 占空比百分之五十LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY fenpin ISPORT (CLK: IN STD_LOGIC;q: OUT STD_LOGIC);END fenpin;ARCHITECTURE arc OF fenpin ISsignal wire:std_logic;BEGIN PROCESS (clk) VARIABLE cnt: INTEGER RANGE 0 TO 31;BEGIN IF clk'EVENT AND clk='1'

2、THENIF cnt<16 THENcnt:=cnt+1;-if cnt=7 then wire<='0'end if; 可以通过这绿色字体修改占空比。ELSE cnt:=0;-q<='1'wire<=not wire;END IF; END IF;END PROCESS;q<=wire;END arc;（2）9进制计数器程序如下LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT9 ISPORT (CLK1,RST,E

3、N : IN STD_LOGIC;CQ : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);END CNT9;ARCHITECTURE behave OF CNT9 ISBEGIN PROCESS (CLK1,RST,EN) VARIABLE CQI : STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN IF RST = '1' THEN CQI := (OTHERS =>'0'); ELSIF CLK1'EVENT AND CLK1='1' THEN IF EN ='1'

4、 THEN IF CQI < 8 THEN CQI := CQI +1; ELSE CQI := (OTHERS =>'0'); END IF; END IF; END IF; CQ <= CQI; END PROCESS; END behave;（3）译码器的程序编写。USE IEEE.STD_LOGIC_1164.ALL;ENTITY DECL7S IS PORT (D:IN STD_LOGIC_VECTOR(3 DOWNTO 0); A:IN STD_LOGIC_VECTOR(2 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(2 D

5、OWNTO 0); LED7S :OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END DECL7S;ARCHITECTURE one OF DECL7S ISBEGIN B <= A; PROCESS(D)BEGINCASE D ISWHEN "0000" => LED7S <= "0111111"WHEN "0001" => LED7S <= "0000110"WHEN "0010" => LED7S <= "10110

6、11"WHEN "0011" => LED7S <= "1001111"WHEN "0100" => LED7S <= "1100110"WHEN "0101" => LED7S <= "1101101"WHEN "0110" => LED7S <= "1111101"WHEN "0111" => LED7S <= "0000111&qu

7、ot;WHEN "1000" => LED7S <= "1111111"WHEN "1001" => LED7S <= "1101111"WHEN OTHERS => NULL;END CASE;END PROCESS;END;将上述三个程序主合成一个通过将32KHz分成1KHz,在译码器上显示数字0到9.的主合程序，需进行元件例化。例化程序如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY KON IS PORT(ain,bin,ci

8、n:IN STD_LOGIC; AN:IN STD_LOGIC_VECTOR(2 DOWNTO 0); BN:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); YOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END KON;ARCHITECTURE one OF KON IS COMPONENT fenpin PORT(CLK:IN STD_LOGIC; Q:OUT STD_LOGIC); END COMPONENT; COMPONENT CNT9 PORT(CLK1,RST,EN:IN STD_LOGIC; CQ:OUT STD_LOGIC_VE

9、CTOR(3 DOWNTO 0); END COMPONENT; COMPONENT DECL7S PORT(D:IN STD_LOGIC_VECTOR(3 DOWNTO 0); A:IN STD_LOGIC_VECTOR(2 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); LED7S:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); END COMPONENT;SIGNAL e:STD_LOGIC;SIGNAL F:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN u1:fenpin PORT MAP(CL

10、K=>ain,Q=>e); u2:CNT9 PORT MAP(CLK1=>e,RST=>bin, EN=>cin,CQ=>F); u3:DECL7S PORT MAP(D=>F,A=>AN,LED7S=>YOUT);END ARCHITECTURE one;具体操作过程如下： File>new>VHDL点击OK即可，再将分频程序粘贴即可，再运行 在新建工程选中New Project wizard.如下图所示开始新建工程如下图所示注意工程名一定要与实体名一致，如fenpin就与实体名一致。单击Next即可弹出如下图再单击Next即可。按下图选好相应的芯片 再单击Next再单击下图Next再单击Next第二个程序以及第三个程序都只需保存编译即可，不许再将工