quartus100全部引脚锁定

1、附录 DE2-115实验板引脚配置信息DE2-115开发板：目标芯片Cyclone IV E EP4CE115F29C7；存储器64MB x2 SDRAM、2MB SRAM、8MB Flash；通信端口：10/100/1000以太网口 x2、USB 2.0时钟：50MHz x3 振荡器、SMA in/out Altera 配置芯片 EPCS64表 1 拨动开关引脚配置Signal NameFPGA Pin No.DescriptionI/O StandardSW0 PIN_AB28Slide Switch0Depending on JP7SW1PIN_AC28Slide Switch1Depe

2、nding on JP7SW2PIN_AC27Slide Switch2Depending on JP7SW3PIN_AD27Slide Switch3Depending on JP7SW4PIN_AB27Slide Switch4Depending on JP7SW5PIN_AC26Slide Switch5Depending on JP7SW6PIN_AD26Slide Switch6Depending on JP7SW7PIN_AB26Slide Switch7Depending on JP7SW8PIN_AC25Slide Switch8Depending on JP7SW9PIN_A

3、B25Slide Switch9Depending on JP7SW10PIN_AC24Slide Switch10Depending on JP7SW11PIN_AB24Slide Switch11Depending on JP7SW12PIN_AB23Slide Switch12Depending on JP7SW13PIN_AA24Slide Switch13Depending on JP7SW14PIN_AA23Slide Switch14Depending on JP7SW15PIN_AA22Slide Switch15Depending on JP7SW16PIN_Y24Slide

4、 Switch16Depending on JP7SW17PIN_Y23Slide Switch17Depending on JP7表 2 按钮开关引脚配置Signal NameFPGA Pin No.DescriptionI/O StandardKEY0PIN_M23Push-button0Depending on JP7KEY1PIN_M21Push-button1Depending on JP7KEY2PIN_N21Push-button2Depending on JP7KEY3PIN_R24Push-button3Depending on JP7表 3 LED 引脚配置Signal N

5、ameFPGA Pin No.DescriptionI/OStandardLEDR0PIN_G19LED Red02.5VLEDR1PIN_F19LED Red12.5VLEDR2PIN_E19LED Red22.5VLEDR3PIN_F21LED Red32.5VLEDR4PIN_F18LED Red42.5VLEDR5PIN_E18LED Red52.5VLEDR6PIN_J19LED Red62.5VLEDR7PIN_H19LED Red72.5VLEDR8PIN_J17LED Red82.5VLEDR9PIN_G17LED Red92.5VLEDR10PIN_J15LED Red102

6、.5VLEDR11PIN_H16LED Red112.5VLEDR12PIN_J16LED Red122.5VLEDR13PIN_H17LED Red132.5VLEDR14PIN_F15LED Red142.5VLEDR15PIN_G15LED Red152.5VLEDR16PIN_G16LED Red162.5VLEDR17PIN_H15LED Red172.5VLEDG0PIN_E21LED Green02.5VLEDG1PIN_E22LED Green12.5VLEDG2PIN_E25LED Green22.5VLEDG3PIN_E24LED Green32.5VLEDG4PIN_H2

7、1LED Green42.5VLEDG5PIN_G20LED Green52.5VLEDG6PIN_G22LED Green62.5VLEDG7PIN_G21LED Green72.5VLEDG8PIN_F17LED Green82.5V表 4 七段数码管引脚配置Signal NameFPGA Pin No.DescriptionI/O StandardHEX00PIN_G18Seven Segment Digit 002.5VHEX01PIN_F22Seven Segment Digit 012.5VHEX02PIN_E17Seven Segment Digit 022.5VHEX03PIN

8、_L26Seven Segment Digit 03Depending on JP7HEX04PIN_L25Seven Segment Digit 04Depending on JP7HEX05PIN_J22Seven Segment Digit 05Depending on JP7HEX06PIN_H22Seven Segment Digit 06Depending on JP7HEX10PIN_M24Seven Segment Digit 10Depending on JP7HEX11PIN_Y22Seven Segment Digit 11Depending on JP7HEX12PIN

9、_W21Seven Segment Digit 12Depending on JP7HEX13PIN_W22Seven Segment Digit 13Depending on JP7HEX14PIN_W25Seven Segment Digit 14Depending on JP7HEX15PIN_U23Seven Segment Digit 15Depending on JP7HEX16PIN_U24Seven Segment Digit 16Depending on JP7HEX20PIN_AA25Seven Segment Digit 20Depending on JP7HEX21PI

10、N_AA26Seven Segment Digit 21Depending on JP7HEX22PIN_Y25Seven Segment Digit 22Depending on JP7HEX23PIN_W26Seven Segment Digit 23Depending on JP7HEX24PIN_Y26Seven Segment Digit 24Depending on JP7HEX25PIN_W27Seven Segment Digit 25Depending on JP7HEX26PIN_W28Seven Segment Digit 26Depending on JP7HEX30P

11、IN_V21Seven Segment Digit 30Depending on JP7HEX31PIN_U21Seven Segment Digit 31Depending on JP7HEX32PIN_AB20Seven Segment Digit 32Depending on JP6HEX33PIN_AA21Seven Segment Digit 33Depending on JP6HEX34PIN_AD24Seven Segment Digit 34Depending on JP6HEX35PIN_AF23Seven Segment Digit 35Depending on JP6HE

12、X36PIN_Y19Seven Segment Digit 36Depending on JP6HEX40PIN_AB19Seven Segment Digit 40Depending on JP6HEX41PIN_AA19Seven Segment Digit 41Depending on JP6HEX42PIN_AG21Seven Segment Digit 42Depending on JP6HEX43PIN_AH21Seven Segment Digit 43Depending on JP6HEX44PIN_AE19Seven Segment Digit 44Depending on

13、JP6HEX45PIN_AF19Seven Segment Digit 45Depending on JP6HEX46PIN_AE18Seven Segment Digit 46Depending on JP6HEX50PIN_AD18Seven Segment Digit 50Depending on JP6HEX51PIN_AC18Seven Segment Digit 51Depending on JP6HEX52PIN_AB18Seven Segment Digit 52Depending on JP6HEX53PIN_AH19Seven Segment Digit 53Dependi

14、ng on JP6HEX54PIN_AG19Seven Segment Digit 54Depending on JP6HEX55PIN_AF18Seven Segment Digit 55Depending on JP6HEX56PIN_AH18Seven Segment Digit 56Depending on JP6HEX60PIN_AA17Seven Segment Digit 60Depending on JP6HEX61PIN_AB16Seven Segment Digit 61Depending on JP6HEX62PIN_AA16Seven Segment Digit 62D

15、epending on JP6HEX63PIN_AB17Seven Segment Digit 63Depending on JP6HEX64PIN_AB15Seven Segment Digit 64Depending on JP6HEX65PIN_AA15Seven Segment Digit 65Depending on JP6HEX66PIN_AC17Seven Segment Digit 66Depending on JP6HEX70PIN_AD17Seven Segment Digit 70Depending on JP6HEX71PIN_AE17Seven Segment Dig

16、it 71Depending on JP6HEX72PIN_AG17Seven Segment Digit 72Depending on JP6HEX73PIN_AH17Seven Segment Digit 73Depending on JP6HEX74PIN_AF17Seven Segment Digit 74Depending on JP6HEX75PIN_AG18Seven Segment Digit 75Depending on JP6HEX76PIN_AA14Seven Segment Digit 763.3V表 5 时钟信号引脚配置信息Signal NameFPGA Pin No

17、.DescriptionI/O StandardCLOCK_50PIN_Y250 MHz clock input3.3VCLOCK2_50PIN_AG1450 MHz clock input3.3VCLOCK3_50PIN_AG1550 MHz clock inputDepending on JP6SMA_CLKOUTPIN_AE23External (SMA) clock outputDepending on JP6SMA_CLKINPIN_AH14External (SMA) clock input3.3V表 6 LCD 模块引脚配置Signal NameFPGAPinNo.Descrip

18、tionI/OLCD_DATA7PIN_M5LCD Data7StandardLCD_DATA6PIN_M3LCD Data63.3VLCD_DATA5PIN_K2LCD Data53.3VLCD_DATA4PIN_K1LCD Data43.3VLCD_DATA3PIN_K7LCD Data33.3VLCD_DATA2PIN_L2LCD Data23.3VLCD_DATA1PIN_L1LCD Data13.3VLCD_DATA0PIN_L3LCD Data03.3VLCD_ENPIN_L4LCD Enable3.3VLCD_RWPIN_M1LCD Read/Write Select, 0 =

19、Write, 1 = Read3.3VLCD_RSPIN_M2LCD Command/Data Select, 0 = Command, 1 = Data3.3VLCD_ONPIN_L5LCD Power ON/OFF3.3VLCD_BLONPIN_L6LCD Back Light ON/OFF3.3V表 7 HSMC 接口引脚配置Signal NameFPGA Pin No.DescriptionI/O StandardHSMC_CLKIN0PIN_AH15Dedicated clock inputDepending on JP6HSMC_CLKIN_N1PIN_J28LVDS RX or

20、CMOS I/O or differential clock inputDepending on JP7HSMC_CLKIN_N2PIN_Y28LVDS RX or CMOS I/O or differential clock inputDepending on JP7HSMC_CLKIN_P1PIN_J27LVDS RX or CMOS I/O or differential clock inputDepending on JP7HSMC_CLKIN_P2PIN_Y27LVDS RX or CMOS I/O or differential clock inputDepending on JP

21、7HSMC_CLKOUT0PIN_AD28Dedicated clock outputDepending on JP7HSMC_CLKOUT_N1 PIN_G24LVDS TX or CMOS I/O or differential clock input/outputDepending on JP7HSMC_CLKOUT_N2 PIN_V24LVDS TX or CMOS I/O or differential clock input/outputDepending on JP7HSMC_CLKOUT_P1 PIN_G23LVDS TX or CMOS I/O or differential

22、 clock input/outputDepending on JP7HSMC_CLKOUT_P2 PIN_V23LVDS TX or CMOS I/O or differential clock input/outputDepending on JP7HSMC_D0PIN_AE26LVDS TX or CMOS I/O Depending on JP7HSMC_D1PIN_AE28LVDS TX or CMOS I/O Depending on JP7HSMC_D2PIN_AE27LVDS TX or CMOS I/O Depending on JP7HSMC_D3PIN_AF27LVDS

23、TX or CMOS I/O Depending on JP7HSMC_RX_D_N0PIN_F25LVDS RX bit 0n or CMOS I/ODepending on JP7HSMC_RX_D_N1PIN_C27LVDS RX bit 1n or CMOS I/ODepending on JP7HSMC_RX_D_N2PIN_E26LVDS RX bit 2n or CMOS I/ODepending on JP7HSMC_RX_D_N3PIN_G26LVDS RX bit 3n or CMOS I/ODepending on JP7HSMC_RX_D_N4PIN_H26LVDS R

24、X bit 4n or CMOS I/ODepending on JP7HSMC_RX_D_N5PIN_K26LVDS RX bit 5n or CMOS I/ODepending on JP7HSMC_RX_D_N6PIN_L24LVDS RX bit 6n or CMOS I/ODepending on JP7HSMC_RX_D_N7PIN_M26LVDS RX bit 7n or CMOS I/ODepending on JP7HSMC_RX_D_N8PIN_R26LVDS RX bit 8n or CMOS I/ODepending on JP7HSMC_RX_D_N9PIN_T26L

25、VDS RX bit 9n or CMOS I/ODepending on JP7HSMC_RX_D_N10PIN_U26LVDS RX bit 10n or CMOS I/ODepending on JP7HSMC_RX_D_N11PIN_L22LVDS RX bit 11n or CMOS I/ODepending on JP7HSMC_RX_D_N12PIN_N26LVDS RX bit 12n or CMOS I/ODepending on JP7HSMC_RX_D_N13PIN_P26LVDS RX bit 13n or CMOS I/ODepending on JP7HSMC_RX

26、_D_N14PIN_R21LVDS RX bit 14n or CMOS I/ODepending on JP7HSMC_RX_D_N15PIN_R23LVDS RX bit 15n or CMOS I/ODepending on JP7HSMC_RX_D_N16PIN_T22LVDS RX bit 16n or CMOS I/ODepending on JP7HSMC_RX_D_P0PIN_F24LVDS RX bit 0 or CMOS I/ODepending on JP7HSMC_RX_D_P1PIN_D26LVDS RX bit 1 or CMOS I/ODepending on J

27、P7HSMC_RX_D_P2PIN_F26LVDS RX bit 2 or CMOS I/ODepending on JP7HSMC_RX_D_P3PIN_G25LVDS RX bit 3 or CMOS I/ODepending on JP7HSMC_RX_D_P4PIN_H25LVDS RX bit 4 or CMOS I/ODepending on JP7HSMC_RX_D_P5PIN_K25LVDS RX bit 5 or CMOS I/ODepending on JP7HSMC_RX_D_P6PIN_L23LVDS RX bit 6 or CMOS I/ODepending on J

28、P7HSMC_RX_D_P7PIN_M25LVDS RX bit 7 or CMOS I/ODepending on JP7HSMC_RX_D_P8PIN_R25LVDS RX bit 8 or CMOS I/ODepending on JP7HSMC_RX_D_P9PIN_T25LVDS RX bit 9 or CMOS I/ODepending on JP7HSMC_RX_D_P10PIN_U25LVDS RX bit 10 or CMOS I/ODepending on JP7HSMC_RX_D_P11PIN_L21LVDS RX bit 11 or CMOS I/ODepending

29、on JP7HSMC_RX_D_P12PIN_N25LVDS RX bit 12 or CMOS I/ODepending on JP7HSMC_RX_D_P13PIN_P25LVDS RX bit 13 or CMOS I/ODepending on JP7HSMC_RX_D_P14PIN_P21LVDS RX bit 14 or CMOS I/ODepending on JP7HSMC_RX_D_P15PIN_R22LVDS RX bit 15 or CMOS I/ODepending on JP7HSMC_RX_D_P16PIN_T21LVDS RX bit 16 or CMOS I/O

30、Depending on JP7HSMC_TX_D_N0PIN_D28LVDS TX bit 0n or CMOS I/ODepending on JP7HSMC_TX_D_N1PIN_E28LVDS TX bit 1n or CMOS I/ODepending on JP7HSMC_TX_D_N2PIN_F28LVDS TX bit 2n or CMOS I/ODepending on JP7HSMC_TX_D_N3PIN_G28LVDS TX bit 3n or CMOS I/ODepending on JP7HSMC_TX_D_N4PIN_K28LVDS TX bit 4n or CMO

31、S I/ODepending on JP7HSMC_TX_D_N5PIN_M28LVDS TX bit 5n or CMOS I/ODepending on JP7HSMC_TX_D_N6PIN_K22LVDS TX bit 6n or CMOS I/ODepending on JP7HSMC_TX_D_N7PIN_H24LVDS TX bit 7n or CMOS I/ODepending on JP7HSMC_TX_D_N8PIN_J24LVDS TX bit 8n or CMOS I/ODepending on JP7HSMC_TX_D_N9PIN_P28LVDS TX bit 9n o

32、r CMOS I/ODepending on JP7HSMC_TX_D_N10PIN_J26LVDS TX bit 10n or CMOS I/ODepending on JP7HSMC_TX_D_N11PIN_L28LVDS TX bit 11n or CMOS I/ODepending on JP7HSMC_TX_D_N12PIN_V26LVDS TX bit 12n or CMOS I/ODepending on JP7HSMC_TX_D_N13PIN_R28LVDS TX bit 13n or CMOS I/ODepending on JP7HSMC_TX_D_N14PIN_U28LV

33、DS TX bit 14n or CMOS I/ODepending on JP7HSMC_TX_D_N15PIN_V28LVDS TX bit 15n or CMOS I/ODepending on JP7HSMC_TX_D_N16PIN_V22LVDS TX bit 16n or CMOS I/ODepending on JP7HSMC_TX_D_P0PIN_D27LVDS TX bit 0 or CMOS I/ODepending on JP7HSMC_TX_D_P1PIN_E27LVDS TX bit 1 or CMOS I/ODepending on JP7HSMC_TX_D_P2P

34、IN_F27LVDS TX bit 2 or CMOS I/ODepending on JP7HSMC_TX_D_P3PIN_G27LVDS TX bit 3 or CMOS I/ODepending on JP7HSMC_TX_D_P4PIN_K27LVDS TX bit 4 or CMOS I/ODepending on JP7HSMC_TX_D_P5PIN_M27LVDS TX bit 5 or CMOS I/ODepending on JP7HSMC_TX_D_P6PIN_K21LVDS TX bit 6 or CMOS I/ODepending on JP7HSMC_TX_D_P7P

35、IN_H23LVDS TX bit 7 or CMOS I/ODepending on JP7HSMC_TX_D_P8PIN_J23LVDS TX bit 8 or CMOS I/ODepending on JP7HSMC_TX_D_P9PIN_P27LVDS TX bit 9 or CMOS I/ODepending on JP7HSMC_TX_D_P10PIN_J25LVDS TX bit 10 or CMOS I/ODepending on JP7HSMC_TX_D_P11PIN_L27LVDS TX bit 11 or CMOS I/ODepending on JP7HSMC_TX_D

36、_P12PIN_V25LVDS TX bit 12 or CMOS I/ODepending on JP7HSMC_TX_D_P13PIN_R27LVDS TX bit 13 or CMOS I/ODepending on JP7HSMC_TX_D_P14PIN_U27LVDS TX bit 14 or CMOS I/ODepending on JP7HSMC_TX_D_P15PIN_V27LVDS TX bit 15 or CMOS I/ODepending on JP7HSMC_TX_D_P16PIN_U22LVDS TX bit 16 or CMOS I/ODepending on JP

37、7表 8 GPIO 引脚配置信息 Signal NameFPGA Pin No.DescriptionI/O StandardGPIO0PIN_AB22GPIO Connection DATA0Depending on JP6GPIO1PIN_AC15GPIO Connection DATA1Depending on JP6GPIO2PIN_AB21GPIO Connection DATA2Depending on JP6GPIO3PIN_Y17GPIO Connection DATA3Depending on JP6GPIO4PIN_AC21GPIO Connection DATA4Depe

38、nding on JP6GPIO5PIN_Y16GPIO Connection DATA5Depending on JP6GPIO6PIN_AD21GPIO Connection DATA6Depending on JP6GPIO7PIN_AE16GPIO Connection DATA7Depending on JP6GPIO8PIN_AD15GPIO Connection DATA8Depending on JP6GPIO9PIN_AE15GPIO Connection DATA9Depending on JP6GPIO10PIN_AC19GPIO Connection DATA10Dep

39、ending on JP6GPIO11PIN_AF16GPIO Connection DATA11Depending on JP6GPIO12PIN_AD19GPIO Connection DATA12Depending on JP6GPIO13PIN_AF15GPIO Connection DATA13Depending on JP6GPIO14PIN_AF24GPIO Connection DATA14Depending on JP6GPIO15PIN_AE21GPIO Connection DATA15Depending on JP6GPIO16PIN_AF25GPIO Connecti

40、on DATA16Depending on JP6GPIO17PIN_AC22GPIO Connection DATA17Depending on JP6GPIO18PIN_AE22GPIO Connection DATA18Depending on JP6GPIO19PIN_AF21GPIO Connection DATA19Depending on JP6GPIO20PIN_AF22GPIO Connection DATA20Depending on JP6GPIO21PIN_AD22GPIO Connection DATA21Depending on JP6GPIO22PIN_AG25G

41、PIO Connection DATA22Depending on JP6GPIO23PIN_AD25GPIO Connection DATA23Depending on JP6GPIO24PIN_AH25GPIO Connection DATA24Depending on JP6GPIO25PIN_AE25GPIO Connection DATA25Depending on JP6GPIO26PIN_AG22GPIO Connection DATA26Depending on JP6GPIO27PIN_AE24GPIO Connection DATA27Depending on JP6GPI

42、O28PIN_AH22GPIO Connection DATA28Depending on JP6GPIO29PIN_AF26GPIO Connection DATA29Depending on JP6GPIO30PIN_AE20GPIO Connection DATA30Depending on JP6GPIO31PIN_AG23GPIO Connection DATA31Depending on JP6GPIO32PIN_AF20GPIO Connection DATA32Depending on JP6GPIO33PIN_AH26GPIO Connection DATA33Dependi

43、ng on JP6GPIO34PIN_AH23GPIO Connection DATA34Depending on JP6GPIO35PIN_AG26GPIO Connection DATA35Depending on JP6表 9 扩展接口引脚配置信息 Signal NameFPGA Pin No.DescriptionI/O StandardEX_IO0PIN_J10Extended IO03.3VEX_IO1PIN_J14Extended IO13.3VEX_IO2PIN_H13Extended IO23.3VEX_IO3PIN_H14Extended IO33.3VEX_IO4PIN_

44、F14Extended IO43.3VEX_IO5PIN_E10Extended IO53.3VEX_IO6PIN_D9Extended IO63.3V表 10 ADV7123 引脚配置Signal NameFPGA Pin No.DescriptionI/O StandardVGA_R0PIN_E12VGA Red03.3VVGA_R1PIN_E11VGA Red13.3VVGA_R2PIN_D10VGA Red23.3VVGA_R3PIN_F12VGA Red33.3VVGA_R4PIN_G10VGA Red43.3VVGA_R5PIN_J12VGA Red53.3VVGA_R6PIN_H

45、8VGA Red63.3VVGA_R7PIN_H10VGA Red73.3VVGA_G0PIN_G8VGA Green03.3VVGA_G1PIN_G11VGA Green13.3VVGA_G2PIN_F8VGA Green23.3VVGA_G3PIN_H12VGA Green33.3VVGA_G4PIN_C8VGA Green43.3VVGA_G5PIN_B8VGA Green53.3VVGA_G6PIN_F10VGA Green63.3VVGA_G7PIN_C9VGA Green73.3VVGA_B0PIN_B10VGA Blue0 3.3VVGA_B1PIN_A10VGA Blue1 3

46、.3VVGA_B2PIN_C11VGA Blue2 3.3VVGA_B3PIN_B11VGA Blue3 3.3VVGA_B4PIN_A11VGA Blue4 3.3VVGA_B5PIN_C12VGA Blue5 3.3VVGA_B6PIN_D11VGA Blue6 3.3VVGA_B7PIN_D12VGA Blue7 3.3VVGA_CLKPIN_A12VGA Clock3.3VVGA_BLANK_NPIN_F11VGA BLANK3.3VVGA_HSPIN_G13VGA H_SYNC3.3VVGA_VSPIN_C13VGA V_SYNC3.3VVGA_SYNC_NPIN_C10VGA SY

47、NC3.3V表 11 音频编解码芯片引脚配置Signal Name FPGA Pin No.DescriptionI/O StandardAUD_ADCLRCKPIN_C2Audio CODEC ADC LR Clock3.3V AUD_ADCDATPIN_D2Audio CODEC ADC Data3.3V AUD_DACLRCKPIN_E3Audio CODEC DAC LR Clock3.3V AUD_DACDATPIN_D1Audio CODEC DAC Data3.3V AUD_XCKPIN_E1Audio CODEC Chip Clock3.3V AUD_BCLKPIN_F2Aud

48、io CODEC Bit-Stream Clock 3.3V I2C_SCLKPIN_B7I2C Clock3.3V I2C_SDATPIN_A8I2C Data3.3V 表 12 RS-232 引脚配置 Signal NameFPGA Pin No.DescriptionI/O StandardUART_RXDPIN_G12UART Receiver3.3VUART_TXDPIN_G9UART Transmitter3.3VUART_CTSPIN_G14UART Clear to Send 3.3VUART_RTSPIN_J13UART Request to Send3.3V表 13 PS/2 引脚配置 Signal NameFPGA Pin No.DescriptionI/O StandardPS2_CLKPIN_G6PS/2 Clock3.3VPS2_DATPIN_H5PS/2 Data3.3VPS2_CLK2PIN_G5PS/2 Clock (reserved for second PS/2 device)3.3VPS2_DAT2PIN_F5PS/2 Data (reserved for second PS/2 device)3.3V表 14 千兆以太网芯片引脚配置