基于的电子闹钟设计

1、（电子行业企业管理）基于的电子闹钟设计基于VHDL的数字闹钟设计摘要：随着EDA技术的发展和应用领域的扩大与深入，EDA技术在电子信息、通信、自动控制及计算机应用领域的重要性日益突出。EDA技术就是依赖功能强大的计算机，在EDA工具软件平台上，对以硬件描述语言VHDL为系统逻辑描述手段完成的设计文件，自动地完成逻辑优化和仿真测试，直至实现既定的电子线路系统功能。本文介绍了基于VHDL硬件描述语言设计的多功能数字闹钟的思路和技巧。在Quartus11开发环境中编译和仿真了所设计的程序，并逐一调试验证程序的运行状况。仿真和验证的结果表明，该设计方法切实可行，该数字闹钟可以实现调时定时闹钟播放音乐功

2、能具有一定的实际应用性。关键字：闹钟FPGAVHDLQuartusII一、电子钟相关功能描述如下：(1)计时功能：这是本计时器设计的基本功能，可进行时、分、秒计时，并显示。(2) 闹钟功能：如果当前时间与设置的闹钟时间相同，则扬声器发出一段音乐，并维持一分钟。(3) 调时调分调闹钟功能：当需要校时或者要重新设置闹钟的时间时，可通过实验箱上的按键控制。二、设计原理：数字闹钟电路的基本结构由两个60进制计数器和一个24进制计数器组成，分别对秒、分、小时进行计时，当计时到23时59分59秒时，再来一个计数脉冲，则计数器清零，重新开始计时。秒计数器的计数时钟CLK为1Hz的标准信号。当数字闹钟处于计时

3、状态时，秒计数器的进位输出信号作为分钟计数器的计数信号，分钟计数器的进位输出信号又作为小时计数器的计数信号时、分、秒的计时结果通过6个数码管来动态显示。数字闹钟除了能够正常计时外，还应能够对时间进行调整。因此，通过模式选择信号KEY1、KEY2控制数字钟的工作状态，即控制数字钟，使其分别工作于正常计时，调整分、时和设定闹钟分、时5个状态。当数字闹钟处于计时状态时，3个计数器允许计数，且秒、分、时计数器的计数时钟信号分别为CLK,秒的进位，分的进位;当数字闹钟处于调整时间状态时，被调的分或时会一秒一秒地增加；当数字钟处于闹钟定时状态时，可以设定小时和分；当计时到所设定的时刻时，speak将会被赋

4、予梁祝音乐信号用于驱动扬声器，持续1分钟。三、实验代码：1)顶层文件：LIBRARYIEEE;USE_LOGIC_1164.ALL;ENTITYclockISPORT(CLK12MHZ:INSTD_LOGIC;CLK8HZ:INSTD_LOGIC;SPKOUT:OUTSTD_LOGIC;CLK:INSTD_LOGIC;KEY1:INSTD_LOGIC;KEY2:INSTD_LOGIC_VECTOR(1DOWNTO0);H1,H2,M1,M2,S1,S2:OUTSTD_LOGIC_VECTOR(3DOWNTO0);END;ARCHITECTUREoneOFclockISCOMPONENTshiz

5、hongPORT(clk:instd_logic;md1:instd_logic;md2:instd_logic_vector(1downto0);clken:outstd_logic;h1,h2,m1,m2,s1,s2:outstd_logic_vector(3downto0);ENDCOMPONENT;COMPONENTNoteTabsPORT(clk:INSTD_LOGIC;ToneIndex:OUTSTD_LOGIC_VECTOR(3DOWNTO0);ENDCOMPONENT;COMPONENTToneTabaPORT(Index:INSTD_LOGIC_VECTOR(3DOWNTO0

6、);Tone:OUTSTD_LOGIC_VECTOR(10DOWNTO0);en:instd_logic);ENDCOMPONENT;COMPONENTSpeakeraPORT(clk:INSTD_LOGIC;Tone:INSTD_LOGIC_VECTOR(10DOWNTO0);SpkS:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALTone:STD_LOGIC_VECTOR(10DOWNTO0);SIGNALToneIndex:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALclken:STD_LOGIC;SIGNALen:STD_LOGIC;BEGIN

7、u1:ShizhongPORTMAP(clk=>CLK,md1=>KEY1,md2=>KEY2,clken=>en,h1=>h1,h2=>h2,m1=>m1,m2=>m2,s1=>s1,s2=>s2);u2:NoteTabsPORTMAP(clk=>CLK8HZ,ToneIndex=>ToneIndex);u3:ToneTabaPORTMAP(Index=>ToneIndex,Tone=>Tone,en=>en);u4:SpeakeraPORTMAP(clk=>CLK12MHZ,Tone=>T

8、one,SpkS=>SPKOUT);END;2)时钟控制模块：libraryieee;use_logic_1164.all;use_logic_;entityshizhongisport(clk:instd_logic;md1:instd_logic;md2:instd_logic_vector(1downto0);clken:outstd_logic;h1,h2,m1,m2,s1,s2:outstd_logic_vector(3downto0);endshizhong;architectureoneofshizhongissignalhou1:std_logic_vector(3dow

9、nto0);signalhou2:std_logic_vector(3downto0);signalmin1:std_logic_vector(3downto0);signalmin2:std_logic_vector(3downto0);signalseth1:std_logic_vector(3downto0);signalseth2:std_logic_vector(3downto0);signalsetm1:std_logic_vector(3downto0);signalsetm2:std_logic_vector(3downto0);signalsec1:std_logic_vec

10、tor(3downto0);signalsec2:std_logic_vector(3downto0);begin小时十位h110:process(clk,hou2,min1,min2,sec1,sec2,md1,md2)beginifclk'eventandclk='1'thenif(hou1="0010"andhou2="0011")and(min1="0101"andmin2="1001")and(sec1="0101"andsec2="1001"

11、;)thenelsifhou1="0010"andhou2="0011"andmd1='0'andmd2="01"then-当时间为23点且处于校时状态时hou1<="0000"elsif(hou2="1001"and(min1="0101"andmin2="1001")and(sec1="0101"andsec2="1001")or(hou2="1001"andmd1=&#

12、39;0'andmd2="01")thenhou1<=hou1+1;endif;endif;endprocessh110;小时个位h220:process(clk,min1,min2,sec1,sec2,md1,md2,hou1)beginifclk'eventandclk='1'thenif(hou1="0010"andhou2="0011")and(min1="0101"andmin2="1001")and(sec1="0101"an

13、dsec2="1001")thenhou2<="0000"elsifhou2="1001"and(min1="0101"andmin2="1001")and(sec1="0101"andsec2="1001")thenhou2<="0000"elsif(hou2="1001"andmd1='0'andmd2="01")or(hou1="0010"an

14、dhou2="0011")thenhou2<="0000"-md<='1'-elsif(min1="0101"andmin2="1001")and(sec1="0101"andsec2="1001")or(md1='0'andmd2="01")thenhou2<=hou2+1;-speak<=clk;-endif;endif;endprocessh220;分钟十位m110:process(clk,mi

15、n2,sec1,sec2,md1,md2)beginifclk'eventandclk='1'thenif(min1="0101"andmin2="1001")and(sec1="0101"andsec2="1001")thenmin1<="0000"elsifmin1="0101"andmin2="1001"and(md1='0'andmd2="00")thenmin1<="

16、;0000"elsif(min2="1001"and(sec1="0101"andsec2="1001")or(min2="1001"andmd1='0'andmd2="00")thenmin1<=min1+1;endif;endif;-endif;endprocessm110;分钟个位m220:process(clk,sec1,sec2,md1,md2)beginifclk'eventandclk='1'thenifmin2="

17、1001"and(sec1="0101"andsec2="1001")thenmin2<="0000"elsifmin2="1001"and(md1='0'andmd2="00")thenmin2<="0000"elseif(sec1="0101"andsec2="1001")or(md1='0'andmd2="00")thenmin2<=min2+1;en

18、dif;endif;endif;endprocessm220;秒十位s110:process(clk)beginifclk'eventandclk='1'thenif(sec1="0101"andsec2="1001")thensec1<="0000"elseifsec2="1001"thensec1<=sec1+1;endif;endif;endif;endprocesss110;秒个位s220:process(clk)beginifclk'eventandclk=&#

19、39;1'thenifsec2="1001"thensec2<="0000"elsesec2<=sec2+1;endif;endif;endprocesss220;时间设置小时部分sethour1:process(clk,seth2)beginifclk'eventandclk='1'thenifseth1="0010"andseth2="0011"thenseth1<="0000"elsifseth2="1001"thens

20、eth1<=seth1+1;endif;endif;endprocesssethour1;sethour2:process(clk,md1,md2,seth1)beginifclk'eventandclk='1'thenif(seth1="0010"andseth2="0011")orseth2="1001"thenseth2<="0000"elsifmd1='1'andmd2="00"thenseth2<=seth2+1;endif;e

21、ndif;endprocesssethour2;时间设置分钟部分setmin1:process(clk,setm2)beginifclk'eventandclk='1'thenifsetm1="0101"andsetm2="1001"thensetm1<="0000"elsifsetm2="1001"thensetm1<=setm1+1;endif;endif;endprocesssetmin1;setmin2:process(clk,md1,md2)beginifclk'

22、;eventandclk='1'thenifsetm2="1001"thensetm2<="0000"elsifmd1='1'andmd2="01"thensetm2<=setm2+1;endif;endif;endprocesssetmin2;闹铃speaker:process(clk,hou1,hou2,min1,min2)beginifclk'eventandclk='1'thenifseth1=hou1andseth2=hou2andsetm1=min1and

23、setm2=min2thenclken<='1'elseclken<='0'endif;endif;endprocessspeaker;disp:process(md1,hou1,hou2,min1,min2,sec1,sec2,seth1,seth2,setm1,setm2)beginifmd1='0'then计时时间显示和设置模式h1<=hou1;h2<=hou2;m1<=min1;m2<=min2;s1<=sec1;s2<=sec2;else闹铃时间现实和设置模式h1<=seth1;h2

24、<=seth2;m1<=setm1;m2<=setm2;s1<="1111"s2<="1111"endif;endprocessdisp;endone;3)乐曲演奏模块：LIBRARYIEEE;USE_LOGIC_1164.ALL;USE_LOGIC_;ENTITYSpeakeraISPORT(clk:INSTD_LOGIC;Tone:INSTD_LOGIC_VECTOR(10DOWNTO0);SpkS:OUTSTD_LOGIC);END;ARCHITECTUREoneOFSpeakeraISSIGNALPreCLK,Ful

25、lSpkS:STD_LOGIC;BEGINDivideCLK:PROCESS(clk)VARIABLECount4:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPreCLK<='0'-将CLK进行16分频，PreCLK为CLK的16分频IFCount4>11THENPreCLK<='1'Count4:="0000"ELSIFclk'EVENTANDclk='1'THENCount4:=Count4+1;ENDIF;ENDPROCESS;GenSpkS:PROCESS(PreCLK,

26、Tone)-11位可预置计数器VARIABLECount11:STD_LOGIC_VECTOR(10DOWNTO0);BEGINIFPreCLK'EVENTANDPreCLK='1'THENIFCount11=16#7FF#THENCount11:=Tone;FullSpkS<='1'ELSECount11:=Count11+1;FullSpkS<='0'ENDIF;ENDIF;ENDPROCESS;DelaySpkS:PROCESS(FullSpkS)-将输出再2分频，展宽脉冲，使扬声器有足够功率发音VARIABLECoun

27、t2:STD_LOGIC;BEGINIFFullSpkS'EVENTANDFullSpkS='1'THENCount2:=NOTCount2;IFCount2='1'THENSpkS<='1'ELSESpkS<='0'ENDIF;ENDIF;ENDPROCESS;END;LIBRARYIEEE;USE_LOGIC_1164.ALL;USE_LOGIC_;ENTITYNoteTabsISPORT(clk:INSTD_LOGIC;ToneIndex:OUTSTD_LOGIC_VECTOR(3DOWNTO0);END

28、;ARCHITECTUREoneOFNoteTabsISCOMPONENTMUSIC-音符数据ROMPORT(address:INSTD_LOGIC_VECTOR(7DOWNTO0);inclock:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(3DOWNTO0);ENDCOMPONENT;SIGNALCounter:STD_LOGIC_VECTOR(7DOWNTO0);BEGINCNT8:PROCESS(clk,Counter)BEGINIFCounter=138THENCounter<="0"ELSIF(clk'EVENTANDclk

29、='1')THENCounter<=Counter+1;ENDIF;ENDPROCESS;u1:MUSICPORTMAP(address=>Counter,q=>ToneIndex,inclock=>clk);END;LIBRARYIEEE;USE_LOGIC_1164.ALL;ENTITYToneTabaISPORT(Index:INSTD_LOGIC_VECTOR(3DOWNTO0);Tone:OUTSTD_LOGIC_VECTOR(10DOWNTO0);en:INSTD_LOGIC);END;ARCHITECTUREoneOFToneTabaISB

30、EGINPROCESS(Index,en)BEGINIFen=,0,THENTone<=""-使能信号ELSECASEIndexlS-译码电路，查表方式，控制音调的预置数WHEN“0000”=>Toneb；WHEN"0001"=>Tone<=""WHEN"0010"=>Tone<=""WHEN"0011"=>Tone<=""WHEN"0101"=>Tone<="&qu

31、ot;WHEN"0110"=>Tone<=""WHEN"0111"=>Tone<=""WHEN"1000"=>Tone<=""WHEN"1001"=>Tone<=""WHEN"1010"=>Tone<=""WHEN"1100"=>Tone<=""WHEN"1101"=

32、>Tone<=""WHEN"1111"=>Tone<=""WHENOTHERS=>NULL;ENDCASE;ENDIF;ENDPROCESS;END;LIBRARYieee;程序USE_logic_1164.all;LIBRARYaltera_mf;USEaltera_mf_;ENTITYmusicISPORT(address:INSTD_LOGIC_VECTOR(7DOWNTO0);inclock:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(3DOWNTO0);ENDmusic;

33、ARCHITECTURESYNOFmusicISSIGNALsub_wire0:STD_LOGIC_VECTOR(3DOWNTO0);COMPONENTaltsyncramGENERIC(intended_device_family:STRING;width_a:NATURAL;widthad_a:NATURAL;numwords_a:NATURAL;operation_mode:STRING;outdata_reg_a:STRING;address_aclr_a:STRING;outdata_aclr_a:STRING;width_byteena_a:NATURAL;init_file:ST

34、RING;lpm_hint:STRING;lpm_type:STRING);PORT(clock0:INSTD_LOGIC;address_a:INSTD_LOGIC_VECTOR(7DOWNTO0);q_a:OUTSTD_LOGIC_VECTOR(3DOWNTO0);ENDCOMPONENT;BEGINq<=sub_wire0(3DOWNTO0);altsyncram_ponent:altsyncramGENERICMAP(intended_device_family=>"Cyclone",width_a=>4,widthad_a=>8,numwords_a=>256,operation_mode=>"ROM",outdata_reg_a=>"UNREGISTERED",address_aclr_a=>"NONE",outdata_aclr_a=>"NONE",width_byteena_a=>1,init_file=>"data1.