本章只要求存储器中的ROM及其用于组合逻辑电路的设计

1、2022-2-16Chapter 9 Memory、CPLD and FPGA本章只要求存储器中的本章只要求存储器中的ROM及其用及其用于组合逻辑电路的设计于组合逻辑电路的设计2022-2-16chapter 92022-2-16chapter 9memorymemoryROM (read-only memory)RAM(random-access memory)Non-volatile while powered downVolatile while powered downOften be used store firmware or initial program of the comp

2、uterData exchange and storing temporarily in CPU or other microprocessormemory：store bits in a structured way2022-2-16chapter 99.1 Read-Only Memory (ROM)9.1 Read-Only Memory (ROM) 1. basic strcture2nb ROMn-bit address inputb-bit data outputA0A1A2An-2An-1D0D1Db-1D0Db-1000n-bit address001111b-bit data

3、sketch map of RAM2022-2-16chapter 92. Internal ROM structurestorage array（Mb）01M-1address input Row (address) decoderA0A1An-1D0Db-1output circuitData output2022-2-16chapter 9word line bit lineaddress decoder输出电路输出电路address inputa data stored unitdata stored arrayData outputhas diode: store 1no diode

4、: store 084 ROM structure2022-2-16chapter 93. Two-dimensional decoding1281ROM000000000011110010000001111111100001111111地址地址2022-2-16chapter 9MOS transistors as storage elementsMOS transistors as storage elements2022-2-16chapter 94. commercial ROM types4. commercial ROM types mask-programmable ROM ar

5、ray connections are programmed during semiconductor manufacture using a mask. very fast. very dense. expensive, 2-4 week turn-around, low power Programmable ROM(PROM) fuses to program once in the field, use PROM programmer, inexpensiveword linebit linefuse2022-2-16chapter 9 EPROM（Erasable PROM） fuse

6、s implemented using floating-gate MOS transistors to program 10k100k times in the field, erased by flooding with UV light. E2PROM（Electrically EPROM） byte-program, individual stored bits may be erased electrically. 2764(8k8), 27128(16k8), 27256(32k8), 27512(64k8) flash E2PROM a specific type of E2PR

7、OM that is erased and programmed in large blocks (NOR type and NAND type)2022-2-16chapter 9floating-gate MOS storage elementsfloating-gate MOS storage elementserased by UV light2022-2-16chapter 9 按照数据的输入按照数据的输入/输出分为串行输出分为串行EEPROM和并和并行行EEPROM。 串行串行EEPROM：在读写数据时，输入：在读写数据时，输入/输出时通过输出时通过2线、线、3线、线、4线或线或S

8、PI总线等接口方式进行的。总线等接口方式进行的。 并行并行EEPROM：数据的输入：数据的输入/输出是通过并行总线输出是通过并行总线进行的。进行的。 近期，低功耗，写入近期，低功耗，写入/擦除速度快的产品很多，擦除速度快的产品很多，如如Microchip公司的新型公司的新型8千位、千位、16千位串行千位串行EEPROM，最快时钟，最快时钟10MHZ，写入时间，写入时间5ms，电流电流3mA,内置写保护功能，可保存数据达内置写保护功能，可保存数据达200年，承受年，承受100万次擦写。万次擦写。Atmel公司的公司的AT24C系列系列2022-2-16chapter 95. Using ROM

9、for “random” combinational logic functions Store the output value of a given truth table in the ROM, the function inputs are connected to the address input .Exp1: the dual polarity decoder.(P.801)POLI1I0Y3 Y2 Y1 Y00000111001101101011010111110100100010101001100010111000184 ROMA0A1A2D0D1D3D2POLI1I0Y0Y

10、1Y2Y32022-2-16chapter 9Exp2: 4Exp2: 44 multiplier4 multiplier每行第一个每行第一个数据单元的数据单元的地址地址每行包含每行包含16个数据单元的数据个数据单元的数据2022-2-16chapter 9More Exp.: ROM在同步时序电路设计中的应用在同步时序电路设计中的应用位序列信号的产生：计数器位序列信号的产生：计数器 ROM法法设计一个码长为设计一个码长为8位的序列信号发生器，信号序列位的序列信号发生器，信号序列为为01111110。CLKCLRLDENPENTDCBAQCQDQBQARCOADD2ADD1ADD0 SEQ V

11、CCCLKD0D1D2D384ROM2022-2-16chapter 9addressQC QB QAROM中存储的数中存储的数据据 D3D0000000000100010100001011000110000011010001110000111100002022-2-16chapter 9ROM在组合电路设计中的应用在组合电路设计中的应用 试用试用84ROM实现如下组合逻辑函数实现如下组合逻辑函数 F1=AB+AC, F2=AB+BC解：先化作标准和式解：先化作标准和式 以输入变量作为以输入变量作为ROM的地址，将输出值的地址，将输出值放入放入ROM单元。单元。 用用16字字4位位ROM实现实

12、现2输入变量的与非、输入变量的与非、或非、异或和同或或非、异或和同或 实现实现4位二进制码位二进制码格雷码的转换格雷码的转换2022-2-16chapter 9Random-access memory (RAM)Random-access memory (RAM)Static RAMDynamic RAMboth are volatileRandom access means:locations in the memory can be written to or read from in any order, regardless of the memory location that wa

13、s last accessed.store a bit of data in the state of a flip-flopstore a bit of data as a charge in a capacitor2022-2-16chapter 99.3 Static Random-Access Memory 2nb RAM structureA0A1Din0An-2An-1D0D1Db-1Dinb-1CSOEWEAddress inputsData inputsControl inputsData outputsD0Db-1000An-1A0001111CS、OE有效，有效，b位数据输

14、出位数据输出CS、WE有效，有效，b位数据输入位数据输入2022-2-16chapter 9SRAM internal structureSRAM internal structureAddress decoderA0A1An-1Storage array(Mb)D0Db-1Output circuit01M-1D0Db-1WR/RDcontrolWE_LCS_LOE_L2022-2-16chapter 9A static-RAM cell SEL_L、WR_L both negated, D latch hold the data； SEL_L is asserted, tri-state

15、buffer enable, data output (read); SEL_L、WR_L both be asserted, D latch open, a new bit is stored.store a bit of data in the state of a flip-flop2022-2-16chapter 9synchronous SRAMsynchronous SRAM A bit of storage is also a latch. Put registers in front of address and control (and maybe data) for eas

16、ier interfacing with synchronous systems at high speeds2022-2-16chapter 99.4 dynamic RAMWrite: Charge the capacitor- store 1;Discharge the capacitor-store 0.Read:- Precharge bit line to VDD/2.- Take the word line HIGH.- Detect whether current flows into or out of the cell.- Note: cell contents are d

17、estroyed by the read!- Must write the bit value back after reading.store a bit of data in a separate capacitor through a MOS transistor, and need to be refreshed periodically.2022-2-16chapter 92022-2-16chapter 9SDRAMSDRAM Control and data operations are referenced to a common clock signal. 是是single

18、data rate, 与系统总线速度同步，在一与系统总线速度同步，在一个时钟周期的上升沿传输一次数据。个时钟周期的上升沿传输一次数据。 曾经是曾经是PC电脑上最为广泛应用的一种电脑上最为广泛应用的一种内存类型内存类型 ，分为分为PC66、PC100、PC133等不同规格，而规等不同规格，而规格后面的数字就代表着该内存最大所能正常工作格后面的数字就代表着该内存最大所能正常工作系统总线速度系统总线速度 2022-2-16chapter 9 双数据传输模式双数据传输模式同步动态随机存储器，即同步动态随机存储器，即DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) 是一种继是一种继SDRAM后产生的后产生的内存内存技术，为具有双技术，为具有双倍数据传输率之倍数据传输率之SDRAM，其数