停车注意事项

1、停車注意事項1.請於研討會中場休息時向主辦單位繳交30元購買停車券，並於離校時將停車券交回警衛室。2.停車時請務必注意凡是”交大教職員工停車格”及”紅黃線區”均不得停車，請務必停放在白線(電資沿路兩旁均為白線區)或其他非員工停車格中。電資大樓1F 第四會議室電資大樓1F 第四會議室 演 講 摘 要 說 明演講者：鍾菁哲名稱：用於低抖動全數位鎖相迴路設計之數位濾波器英文：用A Digital Loop Filter for Low-Jitter All-Digital Phase-Locked Loops摘要：In all-digital PLL design, the PLL controll

2、er continues updating the DCO control code to track the frequency and phase of reference clock to deal with the jitter effects from reference clock, even when PLL is locked,. To minimize the jitter effect, an all-digital filter is proposed to reduce the period jitter of output clock. Thus when PLL c

3、ontroller updates the DCO control code, the proposed all-digital filter keeps tracking the DCO control code, and generates a baseline DCO control code. The PLL controller will adjust the DCO control code around this baseline DCO control code to track the phase/frequency of reference clock in a more

4、efficient way. Compared with the current approaches, the proposed all-digital filter will reduce the peak-to-peak jitter of the reference clock. As a result, the output of the proposed all-digital filter can always have a stable output, and the output jitter of PLL can be minimized as well.演講者：游瑞元名稱

5、：取代外部被動式石英晶體之嵌入式晶體震盪產生器英文：An Embedded Silicon Oscillator for Eliminations of External Passive Crystals摘要：Existing single-chip circuit designs inevitably require a passive external crystal for an accurate reference clock to reach high-speed signal communications. This increases manufacturin

6、g cost, power consumption, and dramatic circuit board area overhead. An embedded silicon oscillator is proposed in this work on a circuit design basis. This generator circuit is portable and can be integrated with any modules that require a reference clock. Potential applications may inclu

7、de wireless/wireline communications, smart analog circuits, high-speed peripheral communications, etc. Consequently, an ASIC or SoC chip with this embedded crystal circuit results in a more compact feasible solution.演講者：余建螢名稱：一個可以容忍製程-電壓-溫度變化及自我校正之時間產生器英文：An Embedded-Crystal Capable of Process-Volta

8、ge-Temperature-Variation Tolerance with Self-Calibration Capability摘要：Among state-of-the-art techniques, there are few oscillators using pure standard CMOS process. The proposed oscillator uses a ring-oscillator-based approach. A key component of the embedded-crystal is

9、 the delay estimator which is able to monitor the absolute delay of the present PVT conditions. This detected delay value is used to calibrate the oscillator that may have the generated frequency changed due to the PVT variations. As a result, the embedded crystal enables accurat

10、e clock frequency without using the external crystal or any RC components. More important, it is fully compatible with standard CMOS process, providing a stable frequency generation under the variations of PVT conditions.演講者： 陳燦文（宋偉豪）名稱：嵌入式晶體震盪產生器系統之震盪頻率調整機制介紹英文：Introduction

11、 to The Clock Mismatch Recovery Behavior in An Embedded Crystal System摘要：An embedded crystal system has benefits of higher CMOS integration, lower power consumptions, and less silicon area. Comparing with a stand-alone crystal system, however, the larger clock mismatch resulting from PVT effects of

12、the embedded crystal is required to be overcome. Hence, a novel design scheme which detects current mismatch information and adjusts the clock frequency of the embedded crystal is proposed to deal with clock mismatch recovery. The detection behavior is performed by mismatch estimations between the l

13、ocal clock frequency and a reference signal that comes from a remote transmitter. With the estimated mismatch in addition to the aid of a PVT detector, the clock frequency of the embedded crystal can be converged with a certain amount that meets wireless communications requirements.演講者：陳俊廷名稱：一個適用於鎖相

14、迴路電路應用之超低功耗遲滯延遲線英文：An Ultra Low Power Hysteresis-Based Delay Line for ADPLL Applications摘要：Digitally controlled oscillator (DCO) is a key module to ADPLL which eliminates the jitter effects from reference clock source. However, the power consumption of DCO occupies more than 50% of ADPLL. For the po

15、wer reduction of ADPLL in embedded-crystal system, a low power hysteresis-based delay cell is proposed in the DCO delay line. Instead of cascading a lot of inverters, the proposed hysteresis delay cells can achieve the same delay value by the smallest area and result in the least static and dynamic

16、power dissipation. Furthermore, the modified hysteresis-based delay cells are also designed for delay resolution improvement in ADPLL applications.演講者：盧台祐名稱： 一個雙頻帶四模式和差調變頻率合成器英文：A Dual-Band Quad-Mode - Frequency Synthesizer摘要：A dual-band, quad-mode - frequency synthesizer for WLAN a,b,g and Bluetoot

17、h applications is presented. Integrating both a multi-modulus PLL and a 3rd order - modulator in a single chip, the channel spacing of the RF synthesizer can be as low as 20 kHz and the frequency hopping time is less than 67 sec. A new charge pump circuit is proposed to improve its linearity and the

18、 matching of the pumping currents. The measured phase noise at 1MHz offset are about -114 dBc/Hz and -116 dBc/Hz respectively at 5 GHz and 2.5 GHz frequency bands. Fabricated in a 0.18-m CMOS process, the chip size is 1.95 mm2. The total power consumption is 19.54 mW from a 1.8 V power supply .主旨：國立交通大學2008年eCrystal技術授權說明會說明：一、依據政府科學技術基本法、行政院國家科學委員會補助學術研發成果管理與推廣作業要點、及行政院暨所屬機關科學技術研究發展成果歸屬與運用準則之規定辦理。二、近年來國家投入大量資源於學術界進行科學技術研究發展，強化學術界的前瞻研發能力提昇產業競爭力，其中在以矽製程為基礎之嵌入式震盪器(eCrystal)研發成果，已可大幅降低設計與製造成本之特性，突破現有應用系統，延伸現階段尚未成形之新應用。eCrystal目前已