电子设计自动化I随堂练习答案

1、电子设计自动化I随堂练习答案第6章VHDL结构与要素1.实体下列实体的语句结构是否正确,如果不正确,请指出具体错误。(1ENTITY mux21 ISPORT(a, b: IN BIT;s: IN BIT;y: OUT BIT;END mux21正确(2ENTITY mux21 ISPORT(a ,b: IN BIT;s: IN BIT;y: OUT BIT;END ENTITY不正确,“END ENTITY mux21”(3entity MUX21 isport(A, B: in bit;S: in bit;Y: out bit;end mux21正确(4ENTITY mux21 ISPOR

2、T(a, b: IN BIT; -a和b分别是数据输入端s: IN BIT;y: OUT BIT;END ENTITY mux21正确(5ENTITY mcu16 ISGENERIC(addrwidth: INTEGER:=16;PORT(add_bus: OUT STD_LOGIC_VECTOR(addrwidth-1 DOWNTO 0;END mcu16正确(6ENTITY mcu8 ISGENERIC(addrwidth: INTEGER:=16;PORT(add_bus: OUT STD_LOGIC_VECTOR(addrwidth-1 DOWNTO 0;END mcu8正确(7ENT

3、ITY mcu16 ISGENERIC(addrwidth: INTEGER;PORT(add_bus: OUT STD_LOGIC_VECTOR(addrwidth-1 DOWNTO 0;END mcu16正确(8ENTITY mcu16 ISGENERIC(addrwidth:=16;PORT(add_bus: OUT STD_LOGIC_VECTOR(addrwidth-1 DOWNTO 0;END mcu16错误,“GENERIC(addrwidth: INTEGER:=16;“(9ENTITY mcu16 ISGENERIC(addrwidth: INTEGER:=16;PORT(a

4、dd_bus: OUT STD_LOGIC_VECTOR(addrwidth-1 DOWNTO 0;END mcu16错误,“GENERIC(addrwidth: INTEGER:=16;“(10ENTITY nand2 ISGENERIC(trise: TIME:=1ns;tfall:TIME:=1ns;PORT(a, b: IN STD_LOGIC;c: OUT STD_LOGIC;END nand2正确(11ENTITY gate4 ISGENERIC(trise: TIME:=1ns;tfall:TIME:=1ns;PORT(a: IN STD_LOGIC;c: OUT STD_LOG

5、IC;d: INOUT STD_LOGIC;e: BUFFER STD_LOGIC;END gate4正确(12ENTITY nand2 ISGENERIC(trise: TIME:=1ns;tfall:TIME:=1ns;PORT(a, b: IN trise;c: OUT tfall;END nand2错误,trise和tfall不是数据类型(13ENTITY nand2 ISGENERIC(trise: TIME:=1ns;tfall:TIME:=1ns;END nand2错误,实体的语句结构必须包含端口说明2.求下列以数制基数表示的文字的十进制数值16#F.11#E2 15x162+1

6、x161+1x160=38578#167.2#E1 1x83+6x82+7x81+2x80=9542#10.0001_1111#E8 1x29+1x24+1x23+1x22+1x21+1x20=543 3.判断下列文字或标识符是否合法“2FFT”合法10#1A# 不合法O"1A”不合法X#E#E2 合法ELSE 不合法Not$ack 不合法_june 不合法june_ 不合法june_ _1 不合法A or B 合法/A or B/ 不合法AB 不合法A/B 合法Enter 合法“1_1101_1000”合法4.数据类型根据要求定义下列常量(CONSTANT、变量(VARIABLE或

7、信号(SIGNALTTL高电平5V,TTL低电平0VCONSTANT TTL_H: REAL:=5.0;CONSTANT TTL_L: REAL:=0.0;a大于b结果为真,a小于b结果为假CONSTANT a_gt_b: BOOLEAN:=TRUE;CONSTANT a_lt_b: BOOLEAN:=FALSE;程序编写者xiaomingCONSTANT editor: STRING:=“xiaoming”;xiaoming的学号201302031111CONSTANT xiaoming_xuehao: STRING:=“201302031111”;xiaoming的EDA考试成绩90分CO

8、NSTANT xiaoming_chengji: INTEGER:=90;8位二进制表示的最大十进制数CONSTANT 8octect_to_integer: INTEGER:=255;用于LED七段码显示数字“9”CONSTANT num_9: BIT_VECTOR:=”1111011”;3-8译码器的输入信号SIGNAL oct_decoder_input: BIT_VECTOR(2 downto 0;D触发器输出信号SIGNAL D_trigger_output: STD_LOGIC;5.赋值语句根据要求给下列变量(VARIABLE或信号(SIGNAL赋值面积a等于a:=3.14*r*r

9、;给8位位矢量的高4位赋值1a(7 downto 4:=”1111”;给8位位矢量的奇数位赋值1a(7:=”1”;a(5:=”1”;a(3:=”1”;a(1:=”1”;开关量信号初值为低电平SIGNAL switch_signal: BIT:=0;EDA考试第一名成绩是99分eda_chengji_1 := 99.0;EDA考试第一名的学号是201302031111eda_xuehao_1 := “201302031111”;负反馈电路信号nf给信号y赋值,传输延迟10nsy<=nf AFTER 10 ns;用变量a给信号y赋值y <=a;将信号y定义为标准逻辑位类型并设置为未初始

10、化的SIGNAL y: STD_LOGIC:=U;6.顺序语句(1根据电路补充VHDL语句ab (aSIGNAL a, b, z: BIT; PROCESS(a, bBEGINIF(a= 0 THENz<=a;ELSIF( b=0 THEN z<=a;ELSEz<=b;END IF;END PROCESS;a b(bSIGNAL a, b, z: BIT; PROCESS(a, bBEGINIF( a = 1 THENz<=1;ELSIF( b = 0 THEN z<=1;ELSEz<=0;END IF;END PROCESS; (cSIGNAL a, b,

11、 c, z: BIT;PROCESS(a, b, cs<= a&b&c ;BEGINCASE s ISWHEN “111 ”=>z<= 1 WHEN OTHERS =>z<=0 END CASE;END PROCESS; (dSIGNAL a, b, c, z: BIT;PROCESS(a, b, cs=a&b&cBEGINCASE s ISWHEN “ 000”|”011”|”101”|”110”=>z<= 0 WHEN OTHERS =>z<= 1 END CASE;END PROCESS;(2根据功能要

12、求写出语句a8位比较器SIGNAL a,b: BIT_VECTOR(7 DOWNTO 0;SIGNAL a_more_or_equal_to_b: BOOLEAN;_a_more_or_equal_to_b <= FALSE;FOR n IN 7 downto 0 LOOPIF( a(n < b(n THENa_more_or_equal_to_b <= FALSE;EXIT;ELSIF( a(n >= b(n THENa_more_or_equal_to_b <= TRUE;EXIT;ELSENULL;END IF;END LOOP;(3根据语句回答问题a(0

13、to 7:=”UUUUUUUU”;b(0 to 15:=” UUUUUUUUUUUUUUUU”;L_x: FOR n IN 0 TO 7 LOOPa(n:=0;k:=0;L_y: LOOPb(k:=0;NEXT L_x WHEN(k>=n;b(k+8:=0;k:=k+1;END LOOP L_y;END LOOP L_x;问上述语句运行结束后变量a和b的值?a(0 to 7:=”00000000”;b(0 to 15:=” 0000000”;7.并行语句(1用并行信号赋值语句改造下列顺序语句 b(aARCHITECTURE a_and_not_b OF mux21 IS SIGNAL a

14、, b, z: BIT;BEGINz<=a WHEN a=0ELSEa WHEN b=0ELSEb;END a_and_not_b; (bARCHITECTURE a_xor_b_xor_c OF xor31 IS SIGNAL a, b, c, z: BIT;BEGINs =a&b&c;WITH s SELECTz<=0WHEN “000”,0WHEN “011”,0WHEN “101”,0WHEN “110”,1WHEN OTHERS ;END a_xor_b_xor_c;(2补充元件例化部分语句实现电路功能 ENTITY or2 ISPORT(a, b: IN BIT;c: out BIT;END or2;ARCHITECTURE or2behv OF or2 ISBEGINc<=a or b;END or2behv;ENTITY or62 ISPORT(a1, b1, a2, b2, a3, b3: IN BIT;z1, z2: out BIT;END or62;ARCHITECTURE or62behv OF or62 ISCOMPONENT or2PORT(a, b: IN BIT;c: out BIT;END COMPON