vhdl的数字钟

1、 基于vhdl的数字钟设计 1、主控模块电路图主控模块代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity control is port(clk,k,set,reset,trans : in std_logic;jh,jm,js,nh,nm,ns,flashh,flashm,flashs,selct :out std_logic);end control;architecture behav of control istyp

2、e states is(s0,s1,s2,s3,s4,s5,s6,s7);signal current_state,next_state :states;beginprocess (reset,clk,next_state,current_state,k,set)beginif (reset='1')thencurrent_state<=s0;elsif(clk'event and clk='1')thencurrent_state<=next_state;end if;case current_state iswhen s0=>fla

3、shh<='0'flashm<='0'flashs<='0'jh<='0'jm<='0'js<='0' nh<='0'nm<='0'ns<='0'selct<='1'if(trans='1')then next_state<=s4;elsif(set='1' ) thennext_state<=s1;elsenext_state<

4、;=s0;end if;when s1=>flashh<='1'flashm<='0'flashs<='0'jh<='1'jm<='0'js<='0' nh<='0'nm<='0'ns<='0'selct<='1'if (set='1')thennext_state<=s2;elsenext_state<=s1;end if;when s2=&

5、gt;flashh<='0'flashm<='1'flashs<='0'jh<='0'jm<='1'js<='0' nh<='0'nm<='0'ns<='0'selct<='1'if (set='1') then next_state<=s3;elsenext_state<=s2;end if;when s3=>flashh<='

6、0'flashm<='0'flashs<='1'jh<='0'jm<='0'js<='1' nh<='0'nm<='0'ns<='0'selct<='1'if ( set='1' ) then next_state<=s0;elsenext_state<=s3;end if;when s4=>flashh<='0'flashm<=

7、'0'flashs<='0'jh<='0'jm<='0'js<='0' nh<='0'nm<='0'ns<='0'selct<='0'if ( trans='1' ) thennext_state<=s0;elsif ( set='1' ) then next_state<=s5;elsenext_state<=s4;end if;when s5=>

8、flashh<='1'flashm<='0'flashs<='0'jh<='0'jm<='0'js<='0' nh<='1'nm<='0'ns<='0'selct<='0'if (set='1') then next_state<=s6;elsenext_state<=s5;end if;when s6=>flashh<='0&#

9、39;flashm<='1'flashs<='0'jh<='0'jm<='0'js<='0' nh<='0'nm<='1'ns<='0'selct<='0'if (set='1' ) thennext_state<=s7;elsenext_state<=s6;end if;when s7=>flashh<='0'flashm<='

10、0'flashs<='1'jh<='0'jm<='0'js<='0' nh<='0'nm<='0'ns<='1'selct<='0'If (set='1') thennext_state<=s4;elsenext_state<=s7;end if;end case;end process;end behav;主控模块仿真图2、计时校时模块计时校时代码二选一library ieee;us

11、e ieee.std_logic_1164.all;entity mux2_1 isport(d0,d1,en :in std_logic; sel :in std_logic; y :out std_logic);end mux2_1;architecture mux2_1_arch of mux2_1 isbegin process(d0,d1,sel) begin if(sel='0')then y<=d0; elsif(sel='1'and en='1')then y<=d1 ; end if; end process;end

12、 mux2_1_arch;六十进制计数library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count_60 isport(clk :in std_logic; qh :buffer std_logic_vector(3 downto 0); ql :buffer std_logic_vector(3 downto 0); co :buffer std_logic);end count_60;architecture behav of count_60 isbegin process(cl

13、k)beginif(rising_edge(clk)thenif(qh="0101"and ql="1001")thenqh<="0000"co<='1'ql<="0000"elsif(ql="1001")thenql<="0000"qh<=qh+1;co<='0'elseql<=ql+1 ;co<='0'end if;end if;end process;end behav;二十

14、四进制计数library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count_24 isport(clk :in std_logic; hh :buffer std_logic_vector(3 downto 0); hl :buffer std_logic_vector(3 downto 0);end count_24;architecture behav of count_24 isbegin process(clk)beginif(rising_edge(clk)thenif(hh=&

15、quot;0010"and hl="0011")thenhh<="0000"hl<="0000"elsif(hl="1001")thenhl<="0000"hh<=hh+1;elsehl<=hl+1;end if;end if;end process;end behav;计时校时仿真图如下3、闹钟设置模块闹钟时间设置模块代码library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.a

16、ll;use ieee.std_logic_unsigned.all;entity clkset isport(hh,hl,mh,ml,sh :in std_logic_vector(3 downto 0); nh,nm,ns,f4 ,k:in std_logic; bhg,bhd,bmg,bmd,bsg,bsd :buffer std_logic_vector(3 downto 0); comout :out std_logic);end clkset ;architecture behav of clkset isbegincom:process(hh,mh,sh,hl,ml)begini

17、f(bhg=hh and bhd=hl and bmg=mh and bmd=ml and bsg=sh)thencomout<='1'elsecomout<='0'end if;end process;set:process(f4)beginif(f4'event and f4='1')thenif(nh='1'and k='1')thenif(bhg="0010" and bhd="0011")thenbhd<="0000"b

18、hg<="0000"elsif(bhd="1001")thenbhd<="0000"bhg<=bhg+1;elsif(bhd<"1001")then bhd<=bhd+1;end if;end if;end if;end process;process(f4)beginif(f4'event and f4='1')thenif(nm='1'and k='1')thenif(bmg="0101" and bmd=

19、"1001")thenbmd<="0000"bmg<="0000"elsif(bmd="1001")thenbmd<="0000"bmg<=bmg+1;elsif(bmd<"1001")then bmd<=bmd+1;end if;end if;end if;end process;process(f4)beginif(f4'event and f4='1')thenif(ns='1' and k=&

20、#39;1')thenif(bsg="0101" and bsd="1001")thenbsd<="0000"bsg<="0000"elsif(bsd="1001")thenbsd<="0000"bsg<=bsg+1;elsif(bsd<"1001")then bsd<=bsd+1;end if;end if;end if;end process;end behav;4、选择显示控制模块显示选择控制模块libra

21、ry ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity compare isport(hh,hl,mh,ml,sh,sl,bhg,bhd,bmg,bmd,bsg,bsd :in std_logic_vector(3 downto 0); flashh,flashm,flashs,clk1,selct :in std_logic; shh,shl,smh,line,sml,ssh,ssl :out std_logic_vector(3 downt

22、o 0);end compare ;architecture behav of compare isbeginline<="1010"process(clk1)beginif selct='1'thenssl<=sl;ssh<=sh;sml<=ml;smh<=mh;shl<=hl;shh<=hh;elsif selct='0'thenssl<=bsd;ssh<=bsg;sml<=bmd;smh<=bmg;shl<=bhd;shh<=bhg;end if;if(clk

23、1='1' and flashs='1')thenssl<="1111"ssh<="1111"end if;if(clk1='1' and flashm='1')thensml<="1111"smh<="1111"end if;if(clk1='1' and flashh='1')thenshl<="1111"shh<="1111"end if;

24、end process;end behav ;5、整点报时及闹钟整点报时及闹钟library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity baoshi isport(mh,ml,sh,sl :in std_logic_vector(3 downto 0); comout,f1024hz,f512hz,clk :in std_logic; bell :out std_logic);end baoshi;architecture behav of baoshi isbeginprocess(clk,

25、mh,ml,sh,sl,f1024hz,f512hz)beginif(comout='1')thenbell<=clk;elsif(mh="0101"and ml="1001" )then if(sh="0101") then if(sl="1001") then bell<=f1024hz; elsif(sl="0001" or sl="0011" or sl="0101" or sl="0111")the

26、n bell<=f512hz; end if; else bell<='0' end if;elsif(ml<"1001"or mh<"0101"or sh<"0101" )then bell<='0'end if;end process;end behav;6、分频模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fenpin isport(clk:in

27、 std_logic; f512,f4,f1:out std_logic);end fenpin;architecture fen of fenpin issignal m:std_logic_vector(9 downto 0);beginprocess(clk)beginif(clk'event and clk='1')thenif m="1111111111"then m<="0000000000"elsem<=m+'1'end if;end if;f512<=m(0); f1<=m(

28、9);f4<=m(7); end process;end fen;分频仿真图7、动态显示模块八选一library ieee;use ieee.std_logic_1164.all;entity mux8_1 isport(D0,D1,D2,D3,D4,D5,D6,D7 :in std_logic_vector(3 downto 0); sel :in std_logic_vector(2 downto 0); Q: out std_logic_vector(3 downto 0);end mux8_1;architecture arch of mux8_1 isbegin process

29、 (D0,D1,D2,D3,D4,D5,D6,D7,SEL)begin case sel iswhen "000"=>Q<=D0;when "001"=>Q<=D1;when "010"=>Q<=D2;when "011"=>Q<=D3;when "100"=>Q<=D4;when "101"=>Q<=D5;when "110"=>Q<=D6;when "111&

30、quot;=>Q<=D7;when others=>Q<="XXXX"end case;end process;end arch;八进制计数器library ieee;use ieee.std_logic_1164.all;entity mux8_1 isport(D0,D1,D2,D3,D4,D5,D6,D7 :in std_logic_vector(3 downto 0); sel :in std_logic_vector(2 downto 0); Q: out std_logic_vector(3 downto 0);end mux8_1;ar

31、chitecture arch of mux8_1 isbegin process (D0,D1,D2,D3,D4,D5,D6,D7,SEL)begin case sel iswhen "000"=>Q<=D0;when "001"=>Q<=D1;when "010"=>Q<=D2;when "011"=>Q<=D3;when "100"=>Q<=D4;when "101"=>Q<=D5;when &qu

32、ot;110"=>Q<=D6;when "111"=>Q<=D7;when others=>Q<="XXXX"end case;end process;end arch;数码管七段显示library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity deled isport( num : in std_logic_vector(3 downto 0); a,b,c,d,e,f,g: out std_logic);en

33、d deled;architecture art of deled is signal led :std_logic_vector(6 downto 0); begin process(num) begin case num is when "0000" => led<="1111110" when "0001" => led<="0110000" when "0010" => led<="1101101" when "0011&

34、quot; => led<="1111001" when "0100" => led<="0110011" when "0101" => led<="1011011" when "0110" => led<="1011111" when "0111" => led<="1110000" when "1000" => led<="1111111" when "1001" => led<="1111011" when "1111" => led<="0000000" when others=> led<="0000001" end case; end process; a<=led(6);b<=led(5);c<=l