VHDL数字电路设计教程第5章习题参考答案

1、第 5 章习题参考答案problem 5.1 library ieee;use ieee.std_logic_1164.all;package my_data_type is constant m: integer :=8;type vector_array is array (natural range<>) of std_logic_vector(m-1 downto 0);end my_data_type;library ieee;use ieee.std_logic_1164.all; use work.my_data_type.all; entity n_mux isge

2、neric (n: integer :=8);port( datain: in vector_array(0 to n-1) ; sel: in integer range 0 to n-1;dataout: out std_logic_vector( m-1 downto 0);end;architecture bhv of n_mux is begindataout<=datain(sel); end;problem 5.2方法一：利用简单赋值语句设计library ieee;use ieee.std_logic_1164.all; entity priority_encoder i

3、sport(x:in std_logic_vector(7 downto 1);y:out std_logic_vector(2 downto 0);end;architecture bhv of priority_encoder is beginy(2)<=x(7) or x(6) or x(5) or x(4);y(1)<=x(7) or x(6) or ( not x(5) and not x(4) and (x(3) or x(2);y(0)<=x(7) or (not x(6) and(x(5) or (not x(4) and (x(3) or (not x(2)

4、 and x(1);end;方法二：利用 when 语句设计library ieee;use ieee.std_logic_1164.all; entity priority_encoder isport(x:in std_logic_vector(7 downto 1);y:out std_logic_vector(2 downto 0);end;architecture bhv of priority_encoder is beginy<="111" when x(7)='1' else"110" when x(6)='

5、1' else "101" when x(5)='1' else "100" when x(4)='1' else "011" when x(3)='1' else "010" when x(2)='1' else "001" when x(1)='1' else "000"end; problem 5.4 library ieee;use ieee.std_logic_1164.all;

6、 use ieee.std_logic_unsigned.all; entity adder8 isport(a,b:in std_logic_vector(7 downto 0); cin:in std_logic;sum:out std_logic_vector(7 downto 0); cout:out std_logic);end;architecture bhv of adder8 issignal a0,b0,cin0, s:std_logic_vector(8 downto 0); begina0<='0'&a; b0<='0'

7、&b; cin0<="00000000"&cin;s<=a0+b0+cin0; sum<=s(7 downto 0); cout<=s(8);end; problem5.5 library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all; use ieee.std_logic_signed.all; entity add_sub isport(a,b:in unsigned(7 downto 0

8、);sel:in bit_vector(1 downto 0);sum:out std_logic_vector(8 downto 0);end;architecture bhv of add_sub issignal temp1,temp2:unsigned (8 downto 0); signal temp3,temp4:signed(8 downto 0);-signal an,as,sn,ss:std_logic_vector(8 downto 0);signal a0,b0:signed (7 downto 0);signal cin0:std_logic_vector(7 down

9、to 0); begina0<=conv_signed(a,8);b0<=conv_signed(b,8); temp1<=conv_unsigned(a+b),9); temp2<=conv_unsigned(a-b),9); temp3<=conv_signed(a0+b0),9); temp4<=conv_signed(a0-b0),9);sum<=conv_std_logic_vector(temp1,9)when sel="00" else conv_std_logic_vector(temp3,9)when sel=&q

10、uot;01" else conv_std_logic_vector(temp2,9)when sel="10" else conv_std_logic_vector(temp4,9);end; problem 5.6 library ieee;use ieee.std_logic_1164.all; entity gray_encoder is generic(n: integer:=4) ;port(input:in std_logic_vector(n-1 downto 0);output:out std_logic_vector(n-1 downto 0)

11、;end;architecture bhv of gray_encoder is beginoutput(n-1)<=input(n-1);output(n-2 downto 0)<=input(n-2 downto 0) xor input(n-1 downto 1); end;problem 5.（7 将原题修改后的作业题， 要求能够实现连续移位， 当 shift信号为 0 时，保持不变，否则每次左移移位，最低位补0，直到全 0为止。）library ieee;use ieee.std_logic_1164.all; entity barrel_shifter isport(i

12、np:in std_logic_vector(7 downto 0); shift: in bit;sel:in integer range 0 to 7;outp:out std_logic_vector(7 downto 0);end;architecture bhv of barrel_shifter istype matrix is array(7 downto 0) of std_logic_vector (7 downto 0); signal row: matrix;beginrow(0)<=inp;l1:for i in 1 to 7 generaterow(i)<

13、=row(0) when shift='0' else row(i-1)(6 downto 0)&'0' ;end generate;outp<=row(sel); end;problem 5.8library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity comp isport(a,b:in integer range 0 to 255; sel:in std_logic; x1,x2,x3:out std_logic);end;architectur

14、e bhv of comp issignal a_signed, b_signed: signed(7 downto 0); signal temp: std_logic_vector (1 to 4);begina_signed<=conv_signed(a,8); b_signed<=conv_signed(b,8); temp(1)<='1' when a>b else'0'temp(2)<='1' when a=b else'0'temp(3)<='1' when a_signed>b_signed else '0'temp(4)<='1&#