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1、White Paper FP GAs for High-Performa nee DSP App licati ons This white paper comp ares the p erforma nee of DSP app licatio ns in Altera FP GAs with popu lar DSP p rocessors as well as comp etitive FPGA offeri ngs. With higher p erforma nee, you can easily time-divisio nm ulti plex your DSP desig n

2、to in crease the nu mber of p rocess ing cha nn els, reduci ng the overall cost of your system. Table 1 shows the p erforma nee adva ntages Altera offers over other silic on solutio ns for DSP systems. Table 1. Altera's VirtexDSP P erforma nee Adva ntage Comp aris on Category Altera FP GAs vs. D

3、SP p rocessorsHigh-performanee FPGAs comparison: Altera ' s Stratix II FPGAs vs. Xilinx -4FPGAs Low-cost FPGAs: Altera ' s Cyclone II FPGAs vs. Xilinx-3 FPGApartanAltera Performanee Advantage 10 DSP>processing power per dollar Up to 1.8 and on- x average 1.2 hXher performanee Up to 2 and

4、oX-average 1.5 higher performaneeFigure 1 comp ares desig n p erforma nee in Altera Stratix II and Cycl one II devices toXili nx Virtex-4 and Sp arta n-3 devices, res pectively. Figure 1. DSP Prop rietary IP &Open Core Results Comp aris on The Stratix II devices achieved an fMAX of over 350MHz i

5、n 9 of the 17 desig ns, and two FIR desig ns exceeded 400 MHz. In comp aris on, only 2 of the 17 desig ns in Virtex-4 devices op erated above 350 MH z. May 2005, ver. 1.1WP-041905-1.1 1FP GAs for High P erforma nee DSP App licati ons Altera Corpo rati on The Cyclone II devices achieved an fMAX of ov

6、er 200 MHz in 9 of the 17 desig ns, and one FIR desig n exceeded 300 MHz. None of the 17 desig ns in Sp arta n-3 devices op erated above 200MHz. P erforma nee Comp aris on Metrics There are many ways to compare the p erforma nee of differe nt DSP soluti ons, and each pro vides a differe nt level of

7、accuracy.The followi ng are three ways to compare DSP p erforma nee. Embedded Mult ip liersP erforma nee: This is a simp listic method for comparing relative DSP p erforma nee that does not take into acco unt the supporting architecture surr ounding the embedded multi pliers and the compi exity and

8、p erforma nee of the overall DSP desig n. This method is the least accurate of the three. DSP IP Ben chmarks: This method is a more accurate p erforma nee comp aris on betwee n differe nt silic on solutio ns because it measures thep erforma nee of popu lar fun cti onal op erati ons that are in tegra

9、l to many DSP desig ns.Fin ite Impu Ise Response (FIR filteri ng and Fast Fourier Tran sforms (FFT are two of the most com mon DSP IP ben chmarks. App licati on Level Ben chmarks: This method p recisely measures the p erforma nee of a p articular silic on soluti on whe n imp leme nti ng a sp ecific

10、app licati on. An exa mple is the ben chmark ing results from Berkeley Desig nTech no logy Inc. (BDTI. The p erforma nee comp aris ons in this white paper use DSP IP ben chmarks and app licati on level ben chmarks. The DSP IP p erforma nee data is based onboth open and proprietary IP cores comparing

11、 Altera' s Stratix II and Cyclone II FPGAs's first generatiorwith Xilinx ' s V-rteand Spartan-3 devices, respectively. The application level ben chmark data is based on real DSP systems for comp aris on of AlteraStratix FP GAs agai nst popular DSP p rocessors. BDTI Ben chmarks - FPGA vs.

12、 DSPP rocessor Berkeley Desig n Tech no logy Inc (BDTI is the lead ing pro vider of independentDSP ben chmarks and p ublishes p eriodic an alysis, FP GAs for DSP, comparing the FPGA's first generationp erforma nee vs. com mon DSP p rocessors. The latest ben chmark based on an orthogo nal freque

13、ncy divisio n mult ip lexi ng (OFDM system shows that AlteraStratix FP GAs pro vide over 95% cost reduct ion per cha nnel comp ared to other DSP processor. (See Table 2. Table 2. BDTI Ben chmark Results on OFDM SystemComparing Stratix FP GAs & Other DSP P rocessors. DSP A Cha nnels Cost (1 ku (1

14、Cost/cha nnel <0.2 $15 $100 DSP B 0.7 $210 $300 Altera Stratix EP 1S20-6 20 $120 $6 Altera Stratix EP 1S80-6 60 $600 $10 Note to Table 2: (1 As of the sec ond quarter of 2005. Results from FP GAs for DSP and unp ublished ben chmarks. Results ?2005 BDTI 2Altera Corporati on FP GAs for High P erfor

15、ma nee DSP App licatio ns OFDMReceiver System In formatio n The ben chmarked OFDM receiver system uses algorithms ranging from table look- ups to MAC-i nte nsive tran sforms. The data sizes ran ges from 4 to 16 bits while the data rate ran ges from 40 to 320 Mbps. Data in eludes real and comp lex va

16、lues. See Figure 2. Figure 2. OFDM System Block Diagram Input and out put p recisi on is 8-bit. This FIR filter in this desig n is a 127-ta p comp lex FIR with real coefficie nts and the FFT is a 256-point complex FFT with input and out put in n atural order. The Slicer is a QAM-256 dema pper. Soft

17、decisi on Viterbi Decoder is used in this desig n. For eve n higher p erforma nee, based on the ben chmark results using real customer desig ns, Altera ' s Stratix II FP GAs offer an average of 50% higher p erforma nee tha nStratix FP GAs. See the Stratix II P erforma nee & Logic Efficie ncy

18、 An alysis White Paper for more details. FPGA vs. FPGA DSP IP p erforma nee ben chmarks compare both high- p erforma nee, high-de nsity FP GAs and low-cost FP GAs. The high-p erforma nee, high- den sity FPGA an alysis com pares Altera Stratix II F PGAs and Xili nx Virtex-4 FP GAs.The low-cost FPGA a

19、n alysis comp ares Altera Cycl one II F PGAs and Xili nx Sp arta n-3FP GAs. The DSP IP p erforma nee ben chmark uses Altera and Xili nx prop rietary IP cores and open cores from www .open . Ben chmark ing Methodology & SetupBen chmark ing an FPGA p erforma nee is a very complex task. A

20、poor ben chmark ing p rocess can p rovide incon elusive and in correct results. Altera has inv ested sig nifica ntly to devel op a rigorous and scie ntific ben chmark ing methodology that is en dorsed by in dustry exp erts as a mea nin gful and accurate way to measure FPGA p erforma nee. For detaile

21、d ben chmark ing methodology, refer to the FPGA P erforma nee Ben chmark ingMethodology White Paper. Table 3 shows the ben chmark set up. 3FP GAs for High P erforma nee DSP AppI icatio ns Altera Corporati on Table 3.Be nchmark Set up FPGA Category High Performa nee FP GAs Low-Cost FP GAs FPGAFamily

22、Altera Stratix II Xili nx Virtex-4 Altera Cyclo ne II Xili nx Sp arta n-3 Sp eed GradeFastest(-3 Fastest(-12 Fastest(-6 Fastest(-5 Syn thesis Tool Prop rietary Open IP CoresCores QIS (1, (2 XST (1, (2 QIS (1, (2 XST (1, (2 Synplify Pro 8.0 Synplify Pro 8.0Synp lify Pro 8.0 Synp lify Pro 8.0 P lace-&

23、amp;-Route Tool Quartus II version 5.0 ISE 7.1iService Pack 1 Quartus II version 5.0 ISE 7.1i Service P ack 1 Notes to Table 3: (1 QISQuartus In tegrated Sy nthesis; XSTXili nx Syn thesis Techn ology (2 FPGA ven dor syn thesis tools are used to comp ile prop rietary cores because these cores are gen

24、 erated net lists and the tool is only res pon sible for sythesiz ing the core wrapper Prop rietary IP &Open Core Desig ns Prop rietary IP cores are cores gen erated from Altera's MegaWizardand Xilinx' s CORE Generator tools. For proprietary IP core comparison, Altera used three types of

25、 com mon DSP IP cores with a total of nine desig ns: FIR filters FFTForward Error Correcti on (FEC These IP cores are gen erated from each FPGA vendor tool and ben chmarked without further manual op timizati on. For open core comp aris on.Altera selected and ben chmarked six differe nt DSP-related o

26、pen IP cores from www .open . Cores are chose n if its popu larity statistics on this web site is greater than 10%. In additi on, the complex FFT core is chose n because it is com monly found inDSP desig ns. The selected open cores are writte n in gen eric HDL code exce pt for the use of FP

27、 GA-s pecific p rimitives in orig inal desig ns, such as in sta ntiati ons of embedded memory blocks and mult ip liers. To allow the comp ilati on of such desig ns for differe ntFP GAs and to pro vide a fair comp aris on, FP GA-s pecific p rimitives in each desig n are conv erted to use the embedded

28、 features of a sp ecific FPGA to achieve the best p erforma nee. After FP GA-s pecific p rimitives are conv erted, the open cores are ben chmarked without futher manual op timizatio n to kee p them as close as p ossible to their origi nal state. More in formatio n for both the prop rietary IP and op

29、en cores is available in the appen dix. High-P erforma nee FPGA Prop rietary IP & Open CoreComparison For high-performanee and highdensity FPGAs, Altera' s Stratix II family offers up-to 1.8 higher performanee, and an average of 1.2 higher performanee, thanXili nx Virtex-4 FP GAs. See Figure

30、 3 for relative p erforma nee comp aris on and Table 4 for detailed p erforma nee data for Stratix II and Virtex-4 families. 4Altera Corporati on FP GAs for High P erforma nee DSP App licatio ns Modern FPGAs embed dedicated mult ip liers to in crease the sp eed of mult iply-accumulate op eratio ns t

31、hat are esse ntial for many DSP desig ns. However, the best system p erforma nee relies on more tha n raw mult ip lier sp eed. It is critical to couple these mult ip liers with a comp leme ntary logic structure and routi ng fabrics of the same p erforma nee. The StratixII family seamlessly in tegrat

32、es DSP blocks that op erate at up to 450 MHz with high performa nee ada ptive logic modules (ALMs and rout ing fabric to offer the highest system p erforma nee for your DSP desig ns. As show n in Figure 1, The Stratix II devicefamily op erated at over 350 MHz in 9 of the 17 desig ns, and two FIR des

33、ig ns exceeded 400 MH z. In comp ariso n, only 2 of the 17 desig ns in Virtex4 devices exceeded 350 MH z, well un der the p erforma nee claimed in the Virtex-4 data sheet. This shows that high system p erforma nee can only be achieved by hav ing an in tellige nt comb in ati on of embedded features a

34、nd fabrics. Figure 3. Stratix II vs. Virtex-4 Prop rietary IP & OpenCore Relative P erforma nee Comp aris on 5Table 4. Detailed Stratix II vs. Virtex-4 DSP Prop rietary IP & Open CoreBen chmark Data P erforma nee Comp aris onDSP IP CateogryDesig n NameStratix II (MHz Virtex-4 (MHz Stratix II

35、/ Virtex-4 Category AverageFIR1 368 306 1.20 FIR2 376 333 1.13 FIR3 450 341 1.32 FIR4 406 322 1.26 FPGAEmbedded DSP Block Based FIR FilterFIR5 368 334 1.101.20 FFT1 389 293 1.33FFT FFT2 393 370 1.06 1.19Reed Solo mon 2841.45Forward Error196Correction (FECViterbi 229 231 0.991.20 AES (Rij ndael231 22

36、2 1.04 1.04 CORDIC 374 366 1.02 1.02Radix 4 Comp lex FFT (CFFT340 270 1.26 1.26 Sim pie FM Receiver (FM 177 99 1.78 1.78 VCS-DCT 231 237 0.97VCS -Huffman Decoder 276 232 1.19 VCS -Huffman Encoder3923441.141.10Open CoresVGA/LCD Con troller 269 246 1.09 1.09Average 1.19Low-Cost FPGA Prop rietary IP &a

37、mp; Open Core Comp arisonAltera ' s -cwst Cyclone II FPGAs offer up to 2 higher performanee, and an average of 1.5 higherp erforma nee, tha n the Xili nx Sp arta n-3 family. Based on the ben chmarked data, theCyclone II device family op erated at over 200 MHz in 9 of the 17 desig ns, and one FIR

38、 desig n exceeded 300 MHz. None of the 17 desig ns in Sp arta n-3 devices op erated above 200 MH z. In additi on, Cycl one II F PGAs out perform Spartan-3 devices in all desig ns ben chmarked. This p erforma nee adva ntage can directly tran slate to higher cha nnel count or lower cost for typ ical d

39、esig ns.Figure 4 shows the relative p erforma nee comp aris on betwee n Cyclone II andSp arta n-3 FP GAs. Table 5 shows detailed p erforma nee data for Cycl one II and Sp arta n-3FP GAs.7Figure 4. Cyclone II vs. Sp arta n-3 Prop rietary DSP IP Core Relative P erforma neeComp aris onTable 5. Detailed

40、 Cyclo ne II vs. Sp arta n-3 DSP Prop rietary IP & Open CoreBen chmark Data P erforma nee Comp aris on DSP IP CateogryDesig n NameCycl one II (MHzSp arta n-3 (MHz Cycl one II / Sp arta n-3CategoryAverageFIR1 258 172 1.50FIR2 314 186 1.68 FIR3 208 186 1.12 FIR4 209 154 1.36 FPGA EmbeddedDSP Block

41、 BasedFIR FilterFIR5 136 (1 (11.40 FFT1 211 144 1.46FFT FFT2 206 174 1.19 1.32Reed Solo mon 1971001.97Forward ErrorCorrection (FECViterbi 172 109 1.571.76 AES (Rij ndael1.181.18CORDIC 246 175 1.40 1.40Radix 4 Comp lex FFT 206 155 1.33 1.33Simp le FM Reciever(FM108 50 2.15 2.15VCS-DCT 1.66 96 1.72 VC

42、S-HuffmanDecoder183 128 1.43 VCS-HuffmanEn coder 266 178 1.501.55 Open CoresVGA/LCDCon troller173 118 1.16 1.46Average 1.48Note to Table 5: (1 The Sp arta n-3 family cannot support the required nu mber of dedicated mult ip liers for this desig n.Con clusi onBased on the ben chmark ing results from B

43、DTI as well as Altera's rigorousben chmark ing methodology, Stratix II and Cycl one II FP GAs pro vide a p erforma neeadva ntage over both popu lar DSP p rocessors and the comp et ing FP GAs. High systemp erforma nee for DSP app licati ons cannot be achieved by simply embeddi ng dedicatedmult ip

44、 liers -it is an aggregate result of high-p erforma nee mult ip liers and p erforma nce-match ing logic structure and rout ing architecture as imp leme nted in Stratix II FP GAs. In addition, Altera ' s Quartus II development software and DSP Builder provide a simpieway to access the DSP p erfor

45、ma nee in Stratix II and Cyclone II FP GAs without time-consuming manual op timizati on.Altera devices pro vide, on average, 10 DSP p rocess ing po wer per dollar tha n the industry ' s most widely used DSP processor solutions.Altera ' s highnsity Stratix II FPGAs offer up to 1.8 and an aver

46、age of 1.2 vhigher p erforma nee tha n Xili nxFfViimexAltera ' s -ewst Cyclone II FPGAs offer up to 2 and an average of 1.5 higherp erforma nee tha n Xili nxs SpfaralyHigher DSP p erforma nee directly tran slates to cost sav ings in typi cal desig ns byin creas ing time-divisi on-m ult ip lexi n

47、g and, therefore, i ncreasi ng the total nu mber ofp rocess ing cha nn els available in your system. Altera offers a comp rehe nsive DSPsoluti on con sisti ng of a comp lete in tegrated software en vir onment, p erforma nce-op timized devices, DSP in tellectual property (IP cores, devel opment kits,

48、 refere needesig ns, and customer trai ning. For more in formatio n, visit p.Appen dix89Prop rietary DSP IP Core In formatio nDSP IP CateogryDesig n Descri pti on & Altera MegaCore IP P arametersDesig n NameTapsClock/ Out put Coefficie nt WidthData WidthCha nnelCoefficie nt SymmetryFIR1 128 64 1

49、6 16 1 Yes FIR2 128 64 8 8 1 Yes FIR3 128 16 8 8 1 Yes FIR4 128 4 8 8 1 Yes FPGA Embedded DSP Block BasedFIR Filter Altera v.3.2.1 Xili nx v.5.1FIR5 128YesDesig n NameArch. PointsDataP recisio nTwiddle Engine Through putEngine #Comp lex Multi plierFFT1 Burst 1024 16-bit 16-bit Quad 1 Sta ndard FFT A

50、ltera v.2.1.2 Xili nx v.3.1FFT2 Streami ng 102416-bit16-bitQuadStan dardDesig nName Pre Setti ngDecodi ng Key Size Bit/ Symbol Symbol/Codeword Check Symbol/ CodewordReed Solo mon Decoder Altera v.3.6.0 Xili nx v.5.1 ReedSolo mon DVB Sta ndardCon ti nu ousHalf20416Desig n NameArchitectureSoft WidthCo

51、n stra int Len gthTrace BackViterbi Decoder Altera v.4.2.0 Xili nx v.5.0Viterbi P arallel66DSP Open Core In formationCore ID Core Name Origi nal URLAESAES (Rjn daelWWW. open /projects.cgi/web/aes_coreCORDIC CORDIC www .open /projects.cgi/web/cordic/overview FMSimple FM Receiverwww. open /projects.cgi/web/sim pl e_fm_receiverVGA VGA/LCD Con tro