北邮数字电路综合实验报告

1、数字电路综合实验报告简易智能密码锁一、实验课题及任务要求密码输入正设计并实现一个数字密码锁，密码锁有四位数字密码和一个确认开锁按键， 确，密码锁打开，密码输入错误进行警示。 基本要求：1、 密码设置：通过键盘进行4位数字密码设定输入，在数码管上显示所输入数字。 通过密码设置确定键（BTN键）进行锁定。2、 开锁：在闭锁状态下，可以输入密码开锁， 且每输入一位密码， 在数码管上显示“-”, 提示已输入密码的位数。输入四位核对密码后，按“开锁”键，若密码正确则系统开锁，若 密码错误系统仍然处于闭锁状态，并用蜂鸣器或led闪烁报警。3、 在开锁状态下，可以通过密码复位键 （BTN键）来清除密码，恢复

2、初始密码“0000”。 闭锁状态下不能清除密码。4、用点阵显示开锁和闭锁状态。 提高要求：，同时1、输入密码数字由右向左依次显示，即：每输入一数字显示在最右边的数码管上 将先前输入的所有数字向左移动一位。2、密码锁的密码位数（46位）可调。3、自拟其它功能。二、系统设计2.1系统总体框图22逻辑流程图2.4分块说明数码管模块，点阵模块，报警模块，防抖模块，控程序主要分为6个模块：键盘模块，制模块。以下进行详细介绍。1.键盘模块然后获取其键值，并对其进行编码，从而进行按键本模块主要完成是 4 X 4键盘扫描， 的识别，并将相应的按键值进行显示。键盘扫描的实现过程如下：对于 4X 4键盘，通常连接

3、为 4行、4列，因此要识别按键， 只需要知道是哪一行和哪一列即可，为了完成这一识别过程，我们的思想是，首先固定输出高电平，在读入输出的行值时，通常高电平会被低电平拉低，当当前位置为高电平“1”时,没有按键按下，否则，如果读入的4行有一位为低电平，那么对应的该行肯定有一个按键按4列为高电平，然后 那么肯定对应的那一列有X789X456X123XX0x（X为无效按键）*消抖键盘译码按键储存键盘扫描下，这样便可以获取到按键的行值。同理，获取列值也是如此，先输出 在输出4行为低电平，再读入列值，如果其中有哪一位为低电平， 按键按下。由此可确定按键位置。2数码管模块本实验采用六位七段共阴极数码管，通过选

4、通 6个位选管脚，向相应的10 口送低电平 来点亮其中任何一位数码管， 因为现在采用四位密码锁， 所以只是用了其中四个， 最高位两 位数码管位选全部置 1.如下附上7段共阴极数码管真值表3.点阵模块点阵模块，共由模式和闭锁模式显示不同的图案, 在有图案下落处的小方格里填上8*8*2个发光二极管组成,行低电平有效，列高电平有效。要求在开锁则先将要显示的每幅图像画8*8个小方格的矩形框中，再“1”，无图案处填上“ 0”，这样就形成了与图案所对应的二巴输出字形Fd1111110rm 1 10110000111101101一 0匚111100130110011011011C1011111r111000

5、011111111厂11111110111 -1 .0,反之亦进制数据在该矩形框上的分布。当闭锁时以红色点阵显示，此时绿色点阵全部置 然。4扌报警模块当报警程序被调用，蜂鸣器输出高电平进行报警，表示输入密码错误5. 防抖按键输入只有为15ms以上的高电平时才会读出按键值从而消除电路中的抖动。6. 控制中心lockmode='1表示关锁，此时点阵显示落锁，按任何键都不会显示密码，清零或者开锁，在此时输入密码 kwei从0开始不断加1,输入的密码位数在数码管上依次左移，当输入密 码m与寄存器中预设密码 mm相同时，按下确认键 btn2切换为开锁状态，lockmode=0 ,此 时按下btn

6、1表示清零，恢复为初始密码0000,按set键寄存器内密码，按下btnioc切换为关锁状态。三、仿真波形分析在QUARTUS2中应用系统自带的功能进行波形仿真，这里采用了分模块仿真。主程序仿真在主要功能程序方面波形如下，在初始化模式按下set键系统进入修改密码状态，setmode波形显示高电平。为仿真方便，仅使kbin （即行输入信号）在 1011和1111两个状态下相互转换，在不同的kbout （即列扫描输出信号）下分别对应4、5、6、7四个数字，故密码寄存器mx为输入的修改后的密码。按下btn2 （确认键）确认密码后，setmode变为低电平，即修改密码状态结束。按下btn1时清零，密码寄

7、存器取值还原为 0000,至此均为开锁状态下的操作，lockmode 一直为低电平。按下闭锁键btnioc后，lockmode从0跳变到1,由此进入闭锁模式。按键消抖模块仿真当按下键时得到的高电平为输入X,持续一定时间后方可输出一个高电平，而无论按下的时间多长，都只输出一个高电平y，从而实现消除按键电路中的抖动。ir T. th爭6弘3弓甲和A】L* I甲坠呷15 CT5 Q5_rLJ"m_n_n_n_ru"T_rT_p_n_rLJLTT_n_rm_rm_n_rLjJ'I""!""3,分频模块仿真为仿真方便，改变分频比。原程序

8、在50Mhz时钟输入下，输出分别为1Mhz、200hzlOOOhz、500hz,分别用于键盘扫描、消抖模块输入、点阵扫描以及数码管扫描。Te u甘ay_wiitivu.t£III01 utIrtfaVir7阿JJl-ta-iler数码管模块仿真第i位选通时，smgzf为mi的七段由smgcatout输出可以看出低四位数码管依次选通。数码管的译码值。II?-*"'n：WWOTM 卜10如 丁"皿JMI 24SlZjHi 翡 HEtrtJ lfi*tViI p>E EE 3T.$S “'S.12 nxD E4cLkkELLcrb-ilenLrJM

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11、dzeolg显示图案； 当loekmode=0时dzeolg全部为0由dzeolr显示图案；而dzrow 直在进行行扫描，形成了两种不同颜色点阵。 报警模块仿真当bj=O时，fmq为0; bj=1时，fmq将elk分频后输出，即蜂鸣器发出声响。l&mHoson 帥HdoflngSinnJMjg r?»ii r馬利上M -咱站 A95罠I Jz.rta:rtcr-Ht I4:jFdlM.1 Pi M二¥ 3<1Q再中句七J 3 衬¥叶 1K,衬J工貿H4,胃gJ轩严H 汩£浮 9ezbjm lis'iueIhjdlkfMimLTOnr

12、mraomTOomwowioTOmjTOfnwiowionmMOfrjurawjioni四、源程序顶层文件library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity lock isport (clk : in std_logic;setmode:out std_logic; lockmode:out std_logic; set:in std_logic;bt n1,bt n2,bt nloc:in std_logic;smgzf: out std_logic_vector(6 dow

13、nto 0); smgcatout:out std_logic_vector(5 dow nto 0); kbin: instd_logic_vector(3 dow nto 0);kbout: buffer std_logic_vector(3 dow nto 0); dzrow,dzcolr,dzcolg: out std_logic_vector(7 dow nto 0); fmq: out std_logic);end lock;setm: std_logic; lockm: std_logic; Ibj: std_logic;architecture behave of lock i

14、ssig nalsig nalsig nal sig nal Ikwei: in teger range 0 to 4;sig nal Im1,lm2,lm3,lm4:i nteger range 0 to 9;-1MHZ-200Hz-1000Hz-500Hz键盘模块sig nal clk_1: std_logic;sig nal clk_2: std_logic;sig nal clk_3: std_logic;sig nal clk_4: std_logic; component kb is port (clk : in std_logic;set:in std_logic;bt n1,b

15、t n2,bt nloc:in std_logic;kbin: in std_logic_vector(3 dow nto 0); kbout: buffer std_logic_vector(3 dow nto 0); bj:out std_logic;setmod:out std_logic; lockmod:out std_logic;kbwei:out in teger range 0 to 4;m1x,m2x,m3x,m4x:out in teger range 0 to 9);end component;component smg is数码管显示模块port (clk : in s

16、td_logic;setmode:i n std_logic; lockmode:i n std_logic; kwei:i n in teger range 0 to 4; m1,m2,m3,m4:in in teger range 0 to 9; smgzf: out std_logic_vector(6 dow nto 0); smgcatout:out std_logic_vector(5 dow nto 0) );end component;component dz is 点阵模块 port (clk : in std_logic;-set:in std_logic;lockmode

17、:i n std_logic;dzrow,dzcolr,dzcolg: out std_logic_vector(7 dow nto 0) );end component;报警模块component alarm is -port (clk : in std_logic;bj:in std_logic;fmq: out std_logic)；end component;component fenpin is 分频模块po rt(clk: in std_logic;clk_out1: out std_logic; clk_out2: out std_logic; clk_out3: out std

18、_logic;clk_out4: out std_logic);end component;begina1: fenpinport ma p(clk=>clk,clk_out1=>clk_1,clk_out2=>clk_2, clk_out3=>clk_3,clk_out4=>clk_4);u1: kbport map(clk=> elk,set => set,btn1 =>bt n1,bt n2=>bt n2,bt nloc=>bt nioc,kbin=>kb in, kbout=>kbout, bj=>lbj,

19、setmod=>setm, lockmod=>lockm, kbwei=>lkwei, m1x=>lm1,m2x=>lm2,m3x=>lm3,m4x=>lm4);u2 :smgport map(clk => clk_4,setmode=>setm,lockmode=>lockm,kwei=>lkwei,m1=>lm1,m2=>lm2,m3=>lm3,m4=>lm4,smgzf=>smgzf,smgcatout=>smgcatout);u3 :dzportmap( clk=>clk_3,l

20、ockmode=>lockm ,dzrow=>dzrow, dzcolr=>dzcolg,dzcolg=>dzcolr );u4 :alarm port map( clk => clk, bj=>lbj, fmq=>fmq); setmode<=setm;lockmode<=lockm;en d;键盘模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity kb isport (clk : in std_logic;set:in

21、 std_logic;bt n1,bt n2,bt nloc:in std_logic;kbin: in std_logic_vector(3 dow nto 0); kbout: buffer std_logic_vector(3 dow nto 0); bj:out std_logic;setmod:out std_logic;lockmod:out std_logic;kbwei:out in teger range 0 to 4; m1x,m2x,m3x,m4x:out in teger range 0 to 9 );end kb;architecture behave of kb i

22、ssig nal jpo ut:i nteger range 0 to 10;sig nal alarm:std_logic;sig nal tmp4: in teger range 0 to 2499999;sig nal clkfd: std_logic;sig nal m1,m2,m3,m4,mm1,mm2,mm3,mm4: in teger range 0 to 9;sig nal wei:i nteger range 0 to 3;sig nal kwei:i nteger range 0 to 4;sig nal setmode:std_logic; sig nal lockmod

23、e:std_logic;sig nal set1:std_logic; sig nal clear: std_logic;sig nal sure: std_logic; sig nal lock: std_logic;sig nal enfini sh: std_logic;sig nal btn 1_out, btn 2_out, btnio c_out, set_out: std_logic;sig nal clk_1: std_logic;-1MHzsig nal clk_2: std_logic;-200Hz component sca n ispo rt(clk_1: in std

24、_logic;clk_2: in std_logic;row: in std_logic_vector(3 dow nto 0); col: buffer std_logic_vector(3 dow nto 0); en_up: buffer std_logic;y: out in teger range 0 to 10);end component;component fenpin is po rt(clk: in std_logic;clk_out1: out std_logic;clk_out2: out std_logic;clk_out3: out std_logic;clk_ou

25、t4: out std_logic); end component;component debo unce is po rt(clk, x: in std_logic; y: out std_logic);end component;beginsetmod<=setmode;lockmod<=lockmode;bj<=alarm;kbwei<=kwei;m1x<=m1;m2x<=m2;m3x<=m3;m4x<=m4;u1: sca n port map( clk_1=>clk_1,clk_2=>clk_2,row=>kb in,

26、col=>kbout,en_up=>en, y=>jpo ut);u2:fenpin portmap (clk=>clk,clk_out1=>clk_1, clk_out2=>clk_2,clk_out3=>open, clk_out4=>open);u3: debo unce port map( clk=>clk_2, x=>bt n1, y=>bt n1_out);u4: debo unce port map( clk=>clk_2, x=>bt n2, y=>bt n2_out);u5: debo unc

27、e port map( clk=>clk_2, x=>bt nl oc, y=>bt nio c_out);u6: debo unce port map( clk=>clk_2, x=>set, y=>set_out);pro cess(clk)beginif(clk'eve nt and clk='1')the nif (tmp4=2499999) thentmp4<=0;clkfd <=not clkfd;elsetmp4 <=t mp 4+1;end if;end if;end pro cess;p roces

28、s(clk_1,e njpo ut)beginif(clk_1'eve nt and clk_1='1') then闭锁状态下输入密码并读入按键值后存入mmif(lockmode='1')the n-wei<=0;if(jpo ut/=10)thenif(kwei=3)the n mm4<=jpo ut;kwei<=kwei+1; elsif(kwei=2)the n mm3<=j po ut;kwei<=kwei+1; elsif(kwei=1)the n mm2<=j po ut;kwei<=kwei+1;

29、elsif(kwei=0)the n mm1<=j po ut;kwei<=kwei+1;end if;end if ;if(sure='1')the n 确认后判断密码是否正确the nif(mm1=m1)a nd(mm2=m2)a nd(mm3=m3)a nd(mm4=m4)lockmode<='0'alarm<='0'正确开锁else kwei<=0;alarm<='1'错误报警end if; end if;else kwei<=0;if(lock='1')then

30、- lockmode<='1' else开锁状态下-上锁if(set1='1')then setmode<='1'-else setmode<='0'end if;if(clear='1') the n 清零m1<=0;m2<=0;m3<=0;m4<=0;-mm1<=0;mm2<=0;mm3<=0;mm4<=0; wei<=0;kwei<=0;alarm<='0'elsif(setmode='1')t

31、he nif(jpout/=10)then 修改密码状态下读入按键值存入m并移位if(wei=0)the n m1<=m2;m2<=m3;m3<=m4; m4<=jpo ut;wei<=wei+1; elsif(wei=1)the n m1<=m2;m2<=m3;m3<=m4; m4<=jpo ut;wei<=wei+1; elsif(wei=2)the n m1<=m2;m2<=m3;m3<=m4; m4<=jpo ut;wei<=wei+1; elsif(wei=3)the n m1<=m2;m

32、2<=m3;m3<=m4; m4<=jpo ut;wei<=0;end if;end if;if(sure='1')the n setmode<='0'alarm<='0' end if;end if;end if;end if;end if;end pro cess;修改密码确认后结束修改密码状态pro cess(set,sure)begin if(clkfd'eve nt and clkfd='1')then if(set='1')the n set1<=

33、9;1'end if; if(sure='1')the n set1<='0'end if;end if;end p rocess;修改密码键pro cess(bt n1) beginif(bt n仁'1')then清零键clear<='1' else clear<='0' end if; end pro cess;确认键p rocess(bt n2)beginif(bt n2='1')the nsure<='1'else sure<='

34、0' end if;end pro cess;p rocess(bt nioc)begin闭锁键if(bt nloc='1')then lock<='1'else lock<='0' end if;end pro cess;end;键盘扫描library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity sca n isport(clk_1: in std_logic;-高频(for scan) 1Mhz clkout1 cl

35、k_2: in std_logic;-低频(for debounee) 200hz clkout2 row: in std_logic_vector(3 dow nto 0);col: buffer std_logic_vector(3 dow nto 0);en_up: out std_logic;y: out in teger range 0 to 10);end sca n;architecture a of sca n issig nal en: std_logic; component debo unce is po rt(clk, x: in std_logic; y: out s

36、td_logic); end component;beginu1: debo unce port map( clk=>clk_2, x=>e n, y=>e n_up); p rocess(clk_1) begin列扫描if(clk_1'eve nt and clk_1='1') then if(e n='1') then col<="1000"elsecase col iswhe n "1110" => col<="1101"whe n "1101

37、" => col<="1011"whe n "1011" => col<="1110"whe n others => col<="1110" end case;end if;end if;end pro cess;p rocess(clk_1, col, row)beginif(clk_1'eve nt and clk_1='1') then case col iswhe n "1000"=>if(row(3) and

38、row(2) and row(1) and row(0)='1') then en <='0'end if;whe n "1110"=>case row is-when "1110" => y<="1111" whe n "1101" =>y<=1; en <='1' whe n "1011" =>y<=4;en <='1'whe n "0111" =&

39、gt;y<=7;en <='1'whe n others => y<=10;-1-4-7-5-8end case;whe n "1101"=>case row is-0-2whe n "1110" =>y<=0; en <='1' when "1101" =>y<=2; en <='1'when "1011" =>y<=5; en <='1' whe n "0

40、111" =>y<=8; en <='1'whe n others =>y<=10;end case;when "1011"=>case row is -when "1110" => y<="1111"when "1101" =>y<=3;en<='1'-3whe n "1011" =>y<=6;en<='1'-6whe n "0111"

41、; =>y<=9;en<='1'-9whe n others =>y<=10;end case;whe n others => n ull;end case;end if;end pro cess;end a;消抖library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity debo unce isport(clk, x: in std_logic; y: out std_logic);end debo unce;200hz低频时钟arc

42、hitecture a of debo unce istype state is(s0,s1,s2,s3,s4); sig nal p re_s, n ext_s: state;beginp rocess(clk)beginif(clk'eve nt and clk='1') then p re_s<=n ext_s;end if;end pro cess;个状态p rocess( pre_s, x)- begincase pre_s iswhe n s0 =>if(x='1') the nn ext_s<=s1; else输入为连续3

43、个或以上的高电平时，输出一个高电平初始状态s0n ext_s<=sO; end if;y<='0'whe n s1 =>if(x='1') the nn ext_s<=s2;elsen ext_s<=sO; end if;y<='0'whe n s2 =>if(x='1') the nn ext_s<=s3; elsen ext_s<=s0; end if;y<='0'连续3个高电平，输出一个高电平3个以上高电平，不再继续输出高电平whe n s3 =&g

44、t;y<='1' n ext_s<=s4;whe n s4 =>y<='0'if(x='1') the nn ext_s<=s4; elsen ext_s<=s0; end if;end case;end pro cess;end a;分频模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity fenpin isport(clk: in std_logic;clk_out1: out std_lo

45、gic;clk_out2: out std_logic;clk_out3: out std_logic;clk_out4: out std_logic );end fenpin;architecture div of fenpin isconstant div1: integer:=24; -1Mhz，用于键盘扫描 constant div2: integer:=124999; -200hz，用于消抖 constant div3: integer:=24999;- -lOOOhz,用于点阵扫描 constant div4: integer:=49999; -500hz，用于数码管扫描 sig

46、nal c1: in teger range 0 to div1;sig nal c2: in teger range 0 to div2;sig nal c3: in teger range 0 to div3;sig nal c4: in teger range 0 to div4;sig nal temp1: std_logic;sig nal temp2: std_logic;sig nal temp3: std_logic;sig nal temp4: std_logic;beginpro cess(clk)beginif(clk'eve nt and clk='1&

47、#39;) the n if(c1=div1) the ntemp1<=not temp1;c1<=0;elsec1<=c1+1;end if;if(c2=div2) the ntemp2<=not temp2; c2<=0;elsec2<=c2+1;end if;if(c3=div3) thentemp3<=not temp3; c3<=0;elsec3<=c3+1;end if;if(c4=div4) the ntemp4<=not temp4; c4<=0;elsec4<=c4+1;end if;end if;end

48、 pro cess;clk_out1<=te mp1;clk_out2<=tem p2;clk_out3<=tem p3;clk_out4<=te mp4;end div;数码管library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity smg isport (clk : in std_logic;-500hz clkout4setmode:i n std_logic; lockmode:i n std_logic;-四位密码的值编码值kwei:i n in te

49、ger range 0 to 4; m1,m2,m3,m4:in in teger range 0 to 9;smgzf: out std_logic_vector(6 dow nto 0); smgcatout:out std_logic_vector(5 dow nto 0) );end smg;architecture behave of smg issig nal smgcat: in teger range 0 to 5;sig nal m1y,m2y,m3y,m4y:std_logic_vector(6 dow nto 0);begin位选码pro cess(clk)beginif

50、(clk'eve nt and clk='1')then if (smgcat=5)the n smgcat<=0;else smgcat<=smgcat+1;end if;end if;end p rocess;pro cess(setmode,lockmode,smgcat)beginif(lockmode='0')the ncase smgcat is 输入密码值在数码管显示，从左到右whe n 0=>smgcatout<="110111"smgzf<=m1y;whe n 1=>smgcato

51、ut<="111011"smgzf<=m2y;whe n 2=>smgcatout<="111101"smgzf<=m3y;whe n 3=>smgcatout<="111110"smgzf<=m4y;whe n 4=>smgcatout<="111111"whe n 5=>smgcatout<="111111"end case;elsesmgzf<="0000001"输入密码在数码管显示if (k

52、wei=1)the n smgcatout<="111110"elsif (kwei=2)then smgcatout<="111100"elsif (kwei=3)then smgcatout<="111000"elsif (kwei=4)then smgcatout<="110000"else smgcatout<="111111"end if;end if;end pro cess;p rocess(m1)begincase m1 is七段数码管真值表whe

53、n 0=>m1y<="1111110"whe n 1=>m1y<="0110000"whe n 2=>m1y<="1101101"whe n 3=>m1y<="1111001"whe n 4=>m1y<="0110011"whe n 5=>m1y<="1011011"whe n 6=>m1y<="1011111"when 7=>m1y<="111000

54、0"whe n 8=>m1y<="1111111"whe n 9=>m1y<="1111011"whe n others=>m1y<="0000000" end case;end p rocess;pro cess(m2)begincase m2 iswhe n 0=>m2y<="1111110"when 1=>m2y<="0110000"whe n 2=>m2y<="1101101"when

55、3=>m2y<="1111001"whe n 4=>m2y<="0110011"whe n 5=>m2y<="1011011"whe n 6=>m2y<="1011111"when 7=>m2y<="1110000"whe n 8=>m2y<="1111111"whe n 9=>m2y<="1111011" when others=>m2y<="000

56、0000" end case;end p rocess;p rocess(m3)begincase m3 is whe n 0=>m3y<="1111110" when 1=>m3y<="0110000"whe n 2=>m3y<="1101101"whe n 3=>m3y<="1111001"whe n 4=>m3y<="0110011"whe n 5=>m3y<="1011011"whe n

57、 6=>m3y<="1011111"when 7=>m3y<="1110000"whe n 8=>m3y<="1111111"whe n 9=>m3y<="1111011"when others=>m3y<="0000000" end case;end p rocess;p rocess(m4)begincase m4 iswhe n 0=>m4y<="1111110"when 1=>m4y<

58、="0110000"whe n 2=>m4y<="1101101"when 3=>m4y<="1111001"whe n 4=>m4y<="0110011"whe n 5=>m4y<="1011011"whe n 6=>m4y<="1011111"when 7=>m4y<="1110000"whe n 8=>m4y<="1111111"whe n 9=&

59、gt;m4y<="1111011"when others=>m4y<="0000000" end case;end p rocess;end;点阵library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;-lOOOhz clkout3en tity dz isport (clk : in std_logic;lockmode:i n std_logic;dzrow,dzcolr,dzcolg: out std_logic_vector(7 do

60、w nto 0) );end dz;architecture behave of dz issig nal dzcat: in teger range 0 to 7; beginp rocess(clk)beginif(clk'eve nt and clk='1')then if (dzcat=7)the n dzcat<=0;else计数器输出dzcat用于行扫描dzcat<=dzcat+1;end if;end if;end p rocess;pro cess(lockmode,clk)点阵显示闭锁图形beginif(lockmode='1

61、9;)the ncase dzcat iswhe n 0=>dzrow<="01111111"dzcolr<="00000000"dzcolg<="00011000"whe n 1=>dzrow<="10111111"dzcolr<="00000000"dzcolg<="00100100"whe n 2=>dzrow<="11011111"dzcolr<="00000000"dzcolg<="00100100"whe n 3=>dzrow<="11101111"dzcolr<="00000000"dzcolg<="01111110"whe n 4=>dzrow<="11110111"dzcolr<="00000000"dzcolg<="01111110"whe n 5=>dzrow<="11111011"dzcolr<=