自动洗衣机控制器ddpp课程设计

1、电子科技大学数字设计原理与实践课程设计报告题目：自动洗衣机控制器姓名：魏玉峰学号：20121710100091、 任务与要求设计内容：1）进行需求分析，确定总体框架； 2）画出逻辑电路图； 3）对设计电路进行仿真；设计要求：假设自动洗衣机的定时操作顺序是，洗衣10min，排水2min，脱水3min，然后停止。设计出这个自动洗衣机的控制器。设计提示：本设计有4个状态，分别为初始状、洗衣系统、排水系统、和脱水状态。当有复位信号时，系统进入循环控制状态，依次执行操作，可从信号灯观察到所处状态。2、 设计思路的介绍 分析：洗衣机开机后，自动进入循环状态，分别进行洗衣10min，排水2min，脱水3mi

2、n的操作，然后回到待机状态。任意期间输入复位信号都会重新开始进入循环控制状态。LED指示灯与当前操作对应，处于发光状态。 由以上要求可知，所有状态共4种，分别为初始状态、洗衣状态、排水状态、和脱水状态，即用1个74163计时器，输出的状态与上面一一对应，具体见下表：0000待机0001洗衣状态0010洗衣状态0011洗衣状态0100洗衣状态0101洗衣状态0110洗衣状态0111洗衣状态1000洗衣状态1001洗衣状态1010洗衣状态1011排水状态1100排水状态1101脱水状态1110脱水状态1111脱水状态故可根据上表分别选择输出时的74163对应输出接口。三、总体方案的选择 经过多次选

3、择与比较最终选择74163,7400来完成电路实现计时功能。将时钟信号设为1/60hz，即每分钟一个上升沿。电路中采用16个4输入与非门，1个12输入与非门，1个2输入与非门，1个3输入与非门。把每一个4输入与非门的四个角分别于74163的Qd、Qc、Qb、Qa相连，而每一个4输入与非门分别对应一个74163的输出状态。当所输出状态对应了洗衣机状态时，总输出状态将产生变化，从而进行当前操作，具体电路图设计如下： Clk为时钟信号1/60hzInput为开关按钮Clr为复位按钮Standby代表当前为待机状态Washing代表当前为洗衣状态Drainage代表当前为排水状态Dehydration

4、代表当前为洗衣状态四、Verilog HDL 代码module try3(clk,input,clr,Standby,Washing,Drainage,Dehydration);inputclk;inputinput;inputclr;outputStandby;outputWashing;outputDrainage;outputDehydration;wireSYNTHESIZED_WIRE_114;wireSYNTHESIZED_WIRE_115;wireSYNTHESIZED_WIRE_2;wireSYNTHESIZED_WIRE_116;wireSYNTHESIZED_WIRE_11

5、7;wireSYNTHESIZED_WIRE_5;wireSYNTHESIZED_WIRE_6;wireSYNTHESIZED_WIRE_7;wireSYNTHESIZED_WIRE_8;wireSYNTHESIZED_WIRE_9;wireSYNTHESIZED_WIRE_10;wireSYNTHESIZED_WIRE_12;wireSYNTHESIZED_WIRE_13;wireSYNTHESIZED_WIRE_16;wireSYNTHESIZED_WIRE_17;wireSYNTHESIZED_WIRE_18;wireSYNTHESIZED_WIRE_23;wireSYNTHESIZED

6、_WIRE_24;wireSYNTHESIZED_WIRE_25;wireSYNTHESIZED_WIRE_34;wireSYNTHESIZED_WIRE_36;wireSYNTHESIZED_WIRE_38;wireSYNTHESIZED_WIRE_39;wireSYNTHESIZED_WIRE_42;wireSYNTHESIZED_WIRE_43;wireSYNTHESIZED_WIRE_44;wireSYNTHESIZED_WIRE_51;wireSYNTHESIZED_WIRE_53;wireSYNTHESIZED_WIRE_78;wireSYNTHESIZED_WIRE_84;wir

7、eSYNTHESIZED_WIRE_85;wireSYNTHESIZED_WIRE_86;wireSYNTHESIZED_WIRE_88;wireSYNTHESIZED_WIRE_90;wireSYNTHESIZED_WIRE_91;wireSYNTHESIZED_WIRE_118;wireSYNTHESIZED_WIRE_95;wireSYNTHESIZED_WIRE_96;wireSYNTHESIZED_WIRE_97;wireSYNTHESIZED_WIRE_98;wireSYNTHESIZED_WIRE_99;wireSYNTHESIZED_WIRE_100;wireSYNTHESIZ

8、ED_WIRE_101;wireSYNTHESIZED_WIRE_102;wireSYNTHESIZED_WIRE_103;wireSYNTHESIZED_WIRE_104;wireSYNTHESIZED_WIRE_105;wireSYNTHESIZED_WIRE_106;wireSYNTHESIZED_WIRE_107;wireSYNTHESIZED_WIRE_108;wireSYNTHESIZED_WIRE_112;wireSYNTHESIZED_WIRE_113;74163 b2v_inst(.ENT(input),.CLRN(clr),.CLK(clk),.ENP(input),.LD

9、N(input),.QA(SYNTHESIZED_WIRE_115),.QB(SYNTHESIZED_WIRE_116),.QC(SYNTHESIZED_WIRE_117),.QD(SYNTHESIZED_WIRE_114);assignSYNTHESIZED_WIRE_105 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_116);assignSYNTHESIZED_WIRE_2 = SYNTHESIZED_WIRE_117;assignSY

10、NTHESIZED_WIRE_113 = (SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6 & SYNTHESIZED_WIRE_7 & SYNTHESIZED_WIRE_8);assignSYNTHESIZED_WIRE_100 = (SYNTHESIZED_WIRE_9 & SYNTHESIZED_WIRE_10 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_12);assignSYNTHESIZED_WIRE_102 = (SYNTHESIZED_WIRE_13 &

11、; SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_16);assignSYNTHESIZED_WIRE_101 = (SYNTHESIZED_WIRE_17 & SYNTHESIZED_WIRE_18 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_116);assignSYNTHESIZED_WIRE_118 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_115 & SYNTHESI

12、ZED_WIRE_23 & SYNTHESIZED_WIRE_24);assignSYNTHESIZED_WIRE_103 = (SYNTHESIZED_WIRE_25 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_116);assignSYNTHESIZED_WIRE_108 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_1

13、16);assignSYNTHESIZED_WIRE_104 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_34 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_36);assignSYNTHESIZED_WIRE_96 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_38 & SYNTHESIZED_WIRE_39 & SYNTHESIZED_WIRE_116);assignSYNTHESIZED_WIRE_95 = (SYNTHE

14、SIZED_WIRE_114 & SYNTHESIZED_WIRE_42 & SYNTHESIZED_WIRE_43 & SYNTHESIZED_WIRE_44);assignSYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_114;assignSYNTHESIZED_WIRE_7 = SYNTHESIZED_WIRE_117;assignSYNTHESIZED_WIRE_8 = SYNTHESIZED_WIRE_116;assignSYNTHESIZED_WIRE_6 = SYNTHESIZED_WIRE_115;assignSYNTHESI

15、ZED_WIRE_90 = SYNTHESIZED_WIRE_117;assignSYNTHESIZED_WIRE_91 = SYNTHESIZED_WIRE_116;assignSYNTHESIZED_WIRE_97 = (SYNTHESIZED_WIRE_51 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_116);assignSYNTHESIZED_WIRE_88 = SYNTHESIZED_WIRE_114;assignSYNTHESIZED_WIRE_84 = SYNTHESIZ

16、ED_WIRE_114;assignSYNTHESIZED_WIRE_86 = SYNTHESIZED_WIRE_117;assignSYNTHESIZED_WIRE_85 = SYNTHESIZED_WIRE_115;assignSYNTHESIZED_WIRE_51 = SYNTHESIZED_WIRE_114;assignSYNTHESIZED_WIRE_53 = SYNTHESIZED_WIRE_117;assignSYNTHESIZED_WIRE_9 = SYNTHESIZED_WIRE_114;assignSYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE

17、_116;assignSYNTHESIZED_WIRE_10 = SYNTHESIZED_WIRE_115;assignSYNTHESIZED_WIRE_13 = SYNTHESIZED_WIRE_114;assignSYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_116;assignSYNTHESIZED_WIRE_17 = SYNTHESIZED_WIRE_114;assignSYNTHESIZED_WIRE_18 = SYNTHESIZED_WIRE_115;assignSYNTHESIZED_WIRE_25 = SYNTHESIZED_WIRE_114;a

18、ssignSYNTHESIZED_WIRE_43 = SYNTHESIZED_WIRE_117;assignSYNTHESIZED_WIRE_44 = SYNTHESIZED_WIRE_116;assignSYNTHESIZED_WIRE_42 = SYNTHESIZED_WIRE_115;assignSYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_117;assignSYNTHESIZED_WIRE_112 = SYNTHESIZED_WIRE_116;assignSYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_116;assign

19、SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_117;assignSYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_115;assignSYNTHESIZED_WIRE_107 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_78 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_116);assignSYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_116;assignSYNTHESIZED_WIRE_34 =

20、 SYNTHESIZED_WIRE_115;assignSYNTHESIZED_WIRE_78 = SYNTHESIZED_WIRE_115;assignSYNTHESIZED_WIRE_98 = (SYNTHESIZED_WIRE_84 & SYNTHESIZED_WIRE_85 & SYNTHESIZED_WIRE_86 & SYNTHESIZED_WIRE_116);assignSYNTHESIZED_WIRE_99 = (SYNTHESIZED_WIRE_88 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_9

21、0 & SYNTHESIZED_WIRE_91);assignWashing = (SYNTHESIZED_WIRE_118 & SYNTHESIZED_WIRE_118 & SYNTHESIZED_WIRE_118 & SYNTHESIZED_WIRE_95 & SYNTHESIZED_WIRE_96 & SYNTHESIZED_WIRE_97 & SYNTHESIZED_WIRE_98 & SYNTHESIZED_WIRE_99 & SYNTHESIZED_WIRE_100 & SYNTHESIZED_WIRE_101 & SYNTHESIZED_WIRE_102 & SYNTHESIZED_WIRE_103);assignDrainage = (SYNTHESIZED_WIRE_104 & SYNTHESIZED_WIRE_105);assignDehydration =