Lec3 FIR Digital Filters(实时信号处理系统)

1、实时信号处理系统设计与实现实时信号处理系统设计与实现第第3章章 FIR 数字滤波器数字滤波器讲授内容安排l1.数字滤波器和FIR理论 转置结构FIR滤波器 FIR滤波器的对称性 线性相位FIR滤波器l2.FIR滤波器设计 直接窗函数设计法 等纹波设计法l3.常系数FIR滤波器设计 直接FIR设计 转置结构FIR滤波器 用分布式算法设计FIR滤波器 IP核FIR滤波器设计 基于DA和基于RAG的FIR滤波器比较I. 数字滤波器和FIR理论数字滤波器（1）l线性时不变滤波器（Linear Time-Invariant，LTI）l有限脉冲响应滤波器（Finite Impulse Response,

2、FIR）采样数量有限，滤波器在每个采样时刻进行有限次卷积l无限脉冲响应滤波器（Infinite Impulse Response, IIR）1. 滤波器在每个采样时刻进行无限次卷积 kky nx nf nx k f nkf k x nk数字滤波器（2）l模拟滤波器 利用微分方程和Laplace变换进行建模与分析 利用RLC元件和运算放大器实现 可以用作IIR滤波器设计的原型l数字滤波器 是数字信号处理的主要组成部分 正在逐渐替代模拟滤波器 IIR滤波器以模拟滤波器为原型进行设计，FIR滤波器直接用数字方法进行设计FIR滤波器理论（1）l对于输入时间序列xn，常系数L阶FIR滤波器的输出yn为

3、为滤波器的系数，对应FIR滤波器的脉冲响应。l用 Z 域表示F(z)是FIR滤波器的传递函数 10Lky nx nf nf k x nk ,0,1,1f kkL Y zF z X z 10LkkF zf k z直接形式FIR滤波器结构l关键路径： TA ：加法器的延迟，TM ：乘法器的延迟 关键路径延迟：1 TM + (M-1) TA l面积： M-1 个寄存器，M 个乘法器，M-1 个加法器l迟滞： 迟滞为x(0)和y(0), x(1)和y(1),之间的时钟周期数。 0 时钟周期迟滞。l运算复杂度： M 次乘法/采样数 + M-1次加法/采样数x(n)Z-1Z-1Z-1h0h1h2hM-1y

4、(n)FIR滤波器理论（2）lFIR滤波器仅有零点存在，系统稳定 多项式F(z)的根确定零点 CIC滤波器（Cascade Integrator Comb Filter，级联积分梳状滤波器 ）具有递归性，但递归部分产生的极点被非递归部分抵消，只有零点。 非递归实现滤波器均为FIR滤波器，但递归实现滤波器可以是FIR滤波器，也可以是I IR滤波器。转置结构FIR滤波器l转置结构 FIR 滤波器是FIR滤波器的常见实现方式，结构上具有如下优点：不需要给输入xn提供额外的移位寄存器；不需要为了获得高流量而在乘积的加法器树中加入流水线不改变系统功能l构造方法利用信号流图反转，是直接形式FIR滤波器的一

5、种变形：将输入和输出互换；颠倒信号流的方向；1.用分支（fork）替换加法器，反之亦然。转置结构FIR滤波器结构x(n)Z-1Z-1Z-1hM-1hM-2hM-3h0y(n)l采用信号流图反转来缩短关键路径长度 转置结构l关键路径延迟：1 TM + 1 TA l面积：M-1个寄存器，M个乘法器，M-1个加法器l迟滞:0 时钟周期迟滞l运算复杂度：M 次乘法/采样数 + M-1次加法/采样数l缺点：寄存器的大小取决于量化机制x(n)的扇出太多FIR滤波器VHDL设计（1）l举例3.1：可编程FIR滤波器 考虑线性卷积和数据（或系数）的位宽为Bx，滤波器长度为L，对无符号SOP运算提供log2L个

6、保护位，对有符号SOP运算提供(log2L)1个保护位。例如，有符号数据（或系数）的位宽为9，L = 4，则加法器的位宽为9 + 9 + log24 1=19. 10Lky nx nf nf k x nkFIR滤波器VHDL设计（2）- This is a generic FIR filter generator - It uses W1 bit data/coefficients bitsLIBRARY lpm; - Using predefined packagesUSE lpm.lpm_components.ALL;LIBRARY ieee;USE ieee.std_logic_1164

7、.ALL;USE ieee.std_logic_arith.ALL;USE ieee.std_logic_unsigned.ALL;ENTITY fir_gen IS - Interface GENERIC (W1 : INTEGER := 9; - Input bit width W2 : INTEGER := 18;- Multiplier bit width 2*W1 W3 : INTEGER := 19;- Adder width = W2+log2(L)-1 W4 : INTEGER := 11;- Output bit width L : INTEGER := 4; - Filte

8、r length Mpipe : INTEGER := 3- Pipeline steps of multiplier );FIR滤波器VHDL设计（3）PORT ( clk : IN STD_LOGIC; Load_x : IN STD_LOGIC; x_in : IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0); c_in : IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0); y_out : OUT STD_LOGIC_VECTOR(W4-1 DOWNTO 0);END fir_gen;ARCHITECTURE flex OF fir_gen IS

9、 SUBTYPE N1BIT IS STD_LOGIC_VECTOR(W1-1 DOWNTO 0); SUBTYPE N2BIT IS STD_LOGIC_VECTOR(W2-1 DOWNTO 0); SUBTYPE N3BIT IS STD_LOGIC_VECTOR(W3-1 DOWNTO 0); TYPE ARRAY_N1BIT IS ARRAY (0 TO L-1) OF N1BIT; TYPE ARRAY_N2BIT IS ARRAY (0 TO L-1) OF N2BIT; TYPE ARRAY_N3BIT IS ARRAY (0 TO L-1) OF N3BIT; SIGNAL x

10、 : N1BIT; SIGNAL y : N3BIT; SIGNAL c : ARRAY_N1BIT; - Coefficient array SIGNAL p : ARRAY_N2BIT; - Product array SIGNAL a : ARRAY_N3BIT; - Adder array FIR滤波器VHDL设计（4）BEGIN Load: PROCESS - Load data or coefficient BEGIN WAIT UNTIL clk = 1; IF (Load_x = 0) THEN c(L-1) = c_in; - Store coefficient in reg

11、ister FOR I IN L-2 DOWNTO 0 LOOP - Coefficients shift one c(I) = c(I+1); END LOOP; ELSE x Compute sum-of-products BEGIN IF clkevent and (clk = 1) THEN FOR I IN 0 TO L-2 LOOP - Compute the transposed a(I) = (p(I)(W2-1) & p(I) + a(I+1); - filter adds END LOOP; a(L-1) = p(L-1)(W2-1) & p(L-1); -

12、 First TAP has END IF; - only a register y W1, LPM_WIDTHB = W1, LPM_PIPELINE = Mpipe, LPM_REPRESENTATION = SIGNED, LPM_WIDTHP = W2, LPM_WIDTHS = W2) PORT MAP ( clock = clk, dataa = x, datab = c(I), result = p(I); END GENERATE; y_out Interface PORT (clk : IN STD_LOGIC; x : IN BYTE; y : OUT BYTE);END

13、fir_srg;ARCHITECTURE flex OF fir_srg IS SIGNAL tap : ARRAY_BYTE; - Tapped delay line of bytes直接FIR滤波器设计举例（3）BEGIN p1: PROCESS - Behavioral Style BEGIN WAIT UNTIL clk = 1; - Compute output y with the filter coefficients weight. - The coefficients are -1 3.75 3.75 -1. - Division for Altera VHDL is onl

14、y allowed for - powers-of-two values! y = 2 * tap(1) + tap(1) + tap(1) / 2 + tap(1) / 4 + 2 * tap(2) + tap(2) + tap(2) / 2 + tap(2) / 4 - tap(3) - tap(0); FOR I IN 3 DOWNTO 1 LOOP tap(I) = tap(I-1); - Tapped delay line: shift one END LOOP; tap(0) Interface PORT (clk : IN STD_LOGIC; x_in0, x_in1, x_i

15、n2 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); y : OUT INTEGER RANGE 0 TO 63);END dafsm;DA-FIR VHDL设计（2）ARCHITECTURE flex OF dafsm IS TYPE STATE_TYPE IS (s0, s1); SIGNAL state : STATE_TYPE; SIGNAL x0, x1, x2, table_in : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL table_out : INTEGER RANGE 0 TO 7;BEGIN table_in(0) =

16、 x0(0); table_in(1) = x1(0); table_in(2) DA in behavioral style VARIABLE p : INTEGER RANGE 0 TO 63;- temp. register VARIABLE count : INTEGER RANGE 0 TO 3; - counts shifts BEGIN WAIT UNTIL clk = 1; CASE state IS WHEN s0 = - Initialization step state = s1; count := 0; p := 0; x0 = x_in0; x1 = x_in1; x

17、2 - Processing step IF count = 3 THEN - Is sum of product done ? y = p; - Output of result to y and state = s0; - start next sum of product ELSE p := p / 2 + table_out * 4; x0(0) = x0(1); x0(1) = x0(2); x1(0) = x1(1); x1(1) = x1(2); x2(0) = x2(1); x2(1) = x2(2); count := count + 1; state table_in, t

18、able_out = table_out);END flex;DA-FIR VHDL设计（4） 系数2, 3, 1的DA算法LUT实现LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;ENTITY case3 IS PORT ( table_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0); table_out : OUT INTEGER RANGE 0 TO 6);END case3;ARCHITECTURE LCs OF case3 ISBEGIN- This is the D

19、A CASE table for- the 3 coefficients: 2, 3, 1 - automatically generated with dagen.exe - DO NOT EDIT! DA-FIR VHDL设计（5）PROCESS (table_in) BEGIN CASE table_in IS WHEN 000 = table_out table_out table_out table_out table_out table_out table_out table_out table_out = 0; END CASE; END PROCESS;END LCs;基于逻辑

20、单元的DA-FIR实现l低阶FIR滤波器实现采用小规模LUT （FIR阶数L4） ，用逻辑单元实现LUTl高阶FIR滤波器实现像构造低阶FIR一样直接用逻辑单元实现大规模LUT会造成逻辑单元资源紧张，例如2bb规模LUT利用FIR滤波器线性相位特性，可以将低阶FIR的输出相加构成高阶FIR的输出响应LUT实现方式：利用FPGA内部存储模块，如M4K，实现LUT。优点：运算速度恒定，节省布线资源；问题：M4K数量较少，应该节约使用！利用小规模LUT（4输入）和多路选择器构成总线结构实现较大规模LUT1.将较大规模LUT划分成若干小规模LUT实现基于逻辑单元的DA-FIR不同实现方式比较5输入DA

21、表（1）LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;ENTITY case5p IS PORT ( clk : IN STD_LOGIC; table_in : IN STD_LOGIC_VECTOR(4 DOWNTO 0); table_out : OUT INTEGER RANGE 0 TO 25);END case5p;ARCHITECTURE LEs OF case5p IS SIGNAL lsbs : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL msbs0 :

22、 STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL table0out00, table0out01 : INTEGER RANGE 0 TO 25;BEGIN- These are the distributed arithmetic CASE tables for- the 5 coefficients: 1, 3, 5, 7, 9- automatically generated with dagen.exe - DO NOT EDIT!5输入DA表（2） PROCESS BEGIN WAIT UNTIL clk = 1; lsbs(0) = table_in(0

23、); lsbs(1) = table_in(1); lsbs(2) = table_in(2); lsbs(3) = table_in(3); msbs0(0) = table_in(4); msbs0(1) table_out table_out table_out table0out00 table0out00 table0out00 table0out00 table0out00 table0out00 table0out00 table0out00 table0out00 table0out00 table0out00 table0out00 table0out00 table0out

24、00 table0out00 table0out00 table0out00 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 INTEGER ENTITY darom IS - Interface PORT (clk : IN STD_LO

25、GIC; x_in0, x_in1, x_in2 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); y : OUT INTEGER RANGE 0 TO 63);END darom;ARCHITECTURE flex OF darom IS TYPE STATE_TYPE IS (s0, s1); SIGNAL state : STATE_TYPE; SIGNAL x0, x1, x2, table_in, mem : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL table_out : INTEGER RANGE 0 TO 7;采用M4K实现D

26、A FIR 滤波器（2）BEGIN table_in(0) = x0(0); table_in(1) = x1(0); table_in(2) DA in behavioral style VARIABLE p : INTEGER RANGE 0 TO 63; -Temp. register VARIABLE count : INTEGER RANGE 0 TO 3; BEGIN - Counts the shifts WAIT UNTIL clk = 1; CASE state IS WHEN s0 = - Initialization step state = s1; count := 0

27、; p := 0; x0 = x_in0; x1 = x_in1; x2 - Processing step IF count = 3 THEN - Is sum of product done ? y = p; - Output of result to y and state = s0; - start next sum of product ELSE p := p / 2 + table_out * 4; x0(0) = x0(1); x0(1) = x0(2); x1(0) = x1(1); x1(1) = x1(2); x2(0) = x2(1); x2(1) = x2(2); co

28、unt := count + 1; state 3, LPM_WIDTHAD = 3, LPM_OUTDATA = UNREGISTERED, LPM_ADDRESS_CONTROL = UNREGISTERED, LPM_FILE = darom3.mif) PORT MAP ( address = table_in, q = mem); table_out Interface PORT (clk : IN STD_LOGIC; x_in0, x_in1, x_in2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); y : OUT INTEGER RANGE -64 T

29、O 63);END dasign;有符号DA FIR滤波器设计（2）ARCHITECTURE flex OF dasign IS TYPE STATE_TYPE IS (s0, s1); SIGNAL state : STATE_TYPE; SIGNAL table_in : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL x0, x1, x2 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL table_out : INTEGER RANGE -2 TO 4;BEGIN table_in(0) = x0(0); table_in(1) =

30、 x1(0); table_in(2) DA in behavioral style VARIABLE p : INTEGER RANGE -64 TO 63;- Temporary reg. VARIABLE count : INTEGER RANGE 0 TO 4; - Counts the BEGIN - shifts WAIT UNTIL clk = 1; CASE state IS WHEN s0 = - Initialization step state = s1; count := 0; p := 0; x0 = x_in0; x1 = x_in1; x2 - Processin

31、g step IF count = 4 THEN - Is sum of product done? y = p; - Output of result to y and state = s0; - start next sum of product ELSE IF count = 3 THEN - Subtract for last p := p / 2 - table_out * 8; - accumulator step ELSE p := p / 2 + table_out * 8; - Accumulation for END IF; - all other steps FOR k

32、IN 0 TO 2 LOOP - Shift bits x0(k) = x0(k+1); x1(k) = x1(k+1); x2(k) = x2(k+1); END LOOP; count := count + 1; state table_in, table_out = table_out);END flex;有符号DA FIR滤波器设计（4） LE表LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;ENTITY case3s IS PORT ( table_in : IN STD_LOGIC_VECT

33、OR(2 DOWNTO 0); table_out : OUT INTEGER RANGE -2 TO 4);END case3s;ARCHITECTURE LEs OF case3s ISBEGIN- This is the DA CASE table for- the 3 coefficients: -2, 3, 1- automatically generated with dagen.exe - DO NOT EDIT! 有符号DA FIR滤波器设计（5）PROCESS (table_in) BEGIN CASE table_in IS WHEN 000 = table_out table_out table_out table_out table_out table_out table_out table_out table_out Interface PORT (clk : IN STD_LOGIC; x_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); y : OUT INTEGER RANGE -46 TO 44);END dapara;展开结构DA-FIR VHDL 设计（2）ARCHITECTURE flex OF dapara IS SIGNAL x0, x1, x2, x3 : STD_LOGIC_VECTOR(2 DOW