quartusii常见的19个错误28个警告

1、（一）Quartus警告解析1 .Found clock-sensitive change during active clock edge at time<time> on register "<name>"原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。而时钟敏感信号是不能在时钟边沿变化的。其后果为导致结果不措施： 编辑 vector source file2 .Verilog HDL assignment warning at <location>: truncat

2、ed with size <number> to match size of target (<number>原因：在HDL设计中对目标的位数进行了设定，如:reg4:0 a;而默认为32位，将位数裁定到合适的大小措施:如果结果正确，无须加以修正，如果不想看到这个警告，可以改变设定的位数3 .All reachable assignments to data_out（10） assign '0', register removed by optimization原因：经过综合器优化后，输出端口已经不起作用了4 .Following 9 pins have

3、 nothing, GND, or VCC driving datain port -changes to this connectivity may change fitting results原因：第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋0'便会被接地，赋接电源。如果你的设计中这些端口就是这样用的，那便可以不理会这些warning5 .Found pins functioning as undefined clocks and/or memory enables原因：是你作为时钟的 PIN没有约束信息。可以对相应的PIN做一下设定就行了。主要是指你的某

4、些管脚在电路当中起到了时钟管脚的作用，比如flip-flop的clk管脚，而此管脚没有时钟约束，因此 QuartusII把"clkf为未定义的时钟。措施:如果clk不是时钟，可以加 “not clock的约束；如果是，可以在 clock setting当中 加入；在某些对时钟要求不很高的情况下，可以忽略此警告或在这里修 改:Assignments>Timing analysis settings.>Individualclocks.>.6 .Timing characteristics of device EPM570T144C5 are preliminary原因

5、：因为MAXII是比较新的元件在QuartusII中的映序并不是正式版的，要等ServicePack措施：只影响Quartus 的Waveform7 .Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled措施：将 setting 中的 timing Requirements&Option->More Timing setting->setting->Enable Clock Latency 中的 on

6、改成 OFF8 .Warning: Found clock high time violation at 14.8 ns on register"|counter|lpm_counter:count1_rtl_0|dffs11"原因：违反了 steup/hold时间，应该是后仿真，看看波形设置是否和时钟沿符合steup/hold时间措施:在中间加个寄存器可能可以解决问题9 .warning: circuit may not operate.detected 46 non-operational paths clocked by clock clk44 with clock

7、skew larger than data delay原因：时钟抖动大于数据延时，当时钟很快，而if等类的层次过多就会出现这种问题，但这个问题多是在器件的最高频率中才会出现: setting->timing Requirements&Options->Default required fmax改小一些，如改到50MHz10 .Design contains <number> input pin(s) that do not drive logic原因：输入引脚没有驱动逻辑(驱动其他引脚)，所有的输入引脚需要有输入逻辑 措施:如果这种情况是故意的，无须理会，如果非

8、故意，输入逻辑驱动.11 .Warning : Found clock high time violation at 8.9ns on node'TEST3.CLK'原因：FF中输入的PLS的保持时间过短措施：在FF中设置较高的时钟频率12 .Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks - node(s) analyzed as buffer(s) resulting in clock skew原因：如果你用的CPLD只有一组全局时钟时，用全

9、局时钟分频产生的另一个时钟在布线中 当作信号处理，不能保证低的时钟歪斜 (SKEW)。会造成在这个时钟上工作的时序电路不可 靠，甚至每次布线产生的问题都不一样。措施:如果用有两组以上全局时钟的FPGA芯片，可以把第二个全局时钟作为另一个时钟用，可以解决这个问题。13 .Critical Warning: Timing requirements were not met. See Report window for details.原因：时序要求未满足，措施：双击 Compilation Report->Time Analyzer-红色部分（如 clock setup:'clk&#

10、39;等）-> 左键单击list path,查看fmax的SLACK REPORT再根据提示解决，有可能是程序的算法问 题14 .Can't achieve minimum setup and hold requirement <text> along<number> path(s). See Report window for details.原因：时序分析发现一定数量的路径违背了最小的建立和保持时间，与时钟歪斜 有关，一般是由于多时钟引起的措施：禾。用 Compilation Report->Time Analyzer->红色部分(如 cl

11、ockhold:'clk'等)，在slack中观察是hold time为负值还是setup time 为负值， 然后在：Assignment->Assignment Editor->To 中增加时钟名(from node finder) , Assignment Name 中增力口和多时钟有关的 Multicycle 和Multicycle Hold 选项，如hold time为负，可 使 Multicycle hold 的值multicycle,如设为 2 和 1。15 : Can't analyze */*.v is missing原因：试图编译一个不存

12、在的文件，该文件可能被改名或者删除了 措施：不管他，没什么影响16 .Warning: Can't find signal in vector source input pin |whole|clk10m原因：因为你的波形仿真文件( vector source file )中并没有把所有的输入 信号(input pin)加进去，对于每一个输入都需要有激励源的17 .Warning: Using design , which is not specified as a designthe current project, butcontains definitions for 1 des

13、ign units and 1 entities in project Info: Found entity 1: lpm_fifo0原因：模块不是在本项目生成的，而是直接copy 了别的项目的原理图和源程序而生成的，而不是用QUARTUS将文件添加进本项目措施：无须理会，不影响使用18 .Timing characteristics of device <name> are preliminary原因：目前版本的QuartusII只对该器件提供初步的时序特征分析措施：如果坚持用目前的器件，无须理会该警告。关于进一步的时序特征分析会 在后续版本的Quartus得到完善。19 .Ti

14、ming Analysis does not support the analysis of latches as synchronous elements for the currently selected device family原因：用 analyze latches as synchronous elementssetting 可以让 Quaruts II 来分析同步锁存，但目前的器件不支持这个特性措施：无须理会。时序分析可能将锁存器分析成回路。但并不一定分析正确。其后果可能会 导致显示提醒用户：改变设计来消除锁存器20 .Warning:Found xx output pins

15、without output pin load capacitance assignment原因：没有给输出管教指定负载电容措施：该功能用于估算TCO和功耗，可以不理会，也可以在Assignment Editor中为相应的输出管脚指定负载电容，以消除警告21 .Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gatedclocks - node(s) analyzed as buffer(s) resulting in clock skew原因：使用了行波时钟或门控时钟，把触发器的输出当时

16、钟用就会报行波时钟，将组合逻辑的输出当时钟用就会报门控时钟措施：不要把触发器的输出当时钟，不要将组合逻辑的输出当时钟，如果本身如此设计，则无须理会该警告22 .Warning (10268): Verilog HDL information at lcd7106.v(63):Always Construct contains both blocking and non-blocking assignments原因：一个always模块中同时有阻塞和非阻塞的赋值23 Warning: Ignored node in vector source file. Can't find corre

17、sponding node name"class sig2" in design.没有编写testbench文件，或者没有编辑输入变量的值testbench里是元件申明和映 射24 . Warning: Compiler packed, optimized or synthesized away node "temp19". Ignored vector source .一"temp19”被优化掉了25 . Warning: Design contains 2 input pin(s) that do not drive logicWarnin

18、g: No output dependent on input pin "clk"Warning: No output dependent on input pin "sign"输出信号与输入信号无关26 . Warning: Ignored node in vector source file. Can't find corresponding node name "over" in design.在源文件中找不到对应的节点“over) "27 : Warning: No exact pin location as

19、signment(s) for 16 pins of 16 total pins定义的管脚没有和外部的管脚连接.28 : Warning: Ignored locations or region assignments to the following nodesWarning: Node "78ledcom4" is assigned to location or region, but does not exist in design设计中没提到"78ledcom4”,而分配了管脚给它。说明：有时II运行了TCL脚本文件后需要修改，修改后有一些先前分配的管脚不

20、需要了，如果没有delete ,则会出现此提示。解决办法：assignments->pins ,把不用的管脚删除即可(TCL脚本文件里的多余管脚分配 语句最好也一起 delete )。（二）Quartus常见错误分析1. Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated with formal port "class" of mode "out"两者不能连接起来2. E

21、rror: VHDL Interface Declaration error in clk gen.vhd(29): interface object "clk scan of mode out cannot be read. Change object mode to buffer or inout.信号类型设置不对，out当作buffer来定义3. Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen引用的例化元件未定义实体entity "clk_gen

22、"4. Error: VHDL Binding Indication error at freqdetect top.vhd(19): port "class" in design entity does not have std logic vector type that is specified for the same generic in the associated component在相关的元件里没有当前文件所定义的类型5. Error: VHDL error at tongbu.vhd(16): can't infer register f

23、or signal "gate" because signal does not hold its outside clock edge6. Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binary operator "or"7. Error: VHDL Association List error at period counter.vhd(38):actual parameterassigned t

24、o formal parameter "alarm", but formal parameter is not declared 连接表错误，形参"alarm”赋值给实参，形参没定义，可能是形参与实参的位置颠倒了， 规定形参在实参之前。8. Error: Ignored construct behavier at period_counter.vhd(15) because of previous errors因为前一个错误而导致的错误9. Error: VHDL error at period counter.vhd(38): type of identifie

25、r "alarm" does not agree with its usage as std logic type "alarm"的定义类型与使用的类型不一致10. Error: VHDL error at shift_reg.vhd(24): can't synthesize logic for statement with conditions that test for the edges of multiple clocks同一进程中含有两个或多个if(edge)条件，(一个进程中之能有一个时钟沿)11. Error: Can't

26、 resolve multiple constant drivers for net"datain reg22"atshift reg.vhd(19)12. Error: can't infer register for signal "num0" because signal does not hold its outside clock edge13. Error: Can't elaborate top-level user hierarchy14. Error: Error: Can't resolve multiple constant drivers for net "cs in"ated key.vhd(32) 有两个以上赋值语句，不能确定"cs in的值，15. Error: Can't access JTAG chain无法找到下载链16. Error: Can't name logic scfifo0 of instance "inst" -has same name as current des