西电eda大作业

1、多频双控彩灯设计电院021215班02121422李明阳一、 课题选择本次vhdl程序设计的题目我选择的是彩灯设计，命题如下：彩灯控制器1设计要求设计能让一排灯（8只）自动改变显示花样的控制系统。可将实验板上的一排发光二极管作为彩灯用。控制器应有两种控制方式：规则变化。变化节拍有0.5秒和0.25秒两种,交替出现,每种节拍可有8种花样,各执行一或二个周期后轮换。彩灯变化方向有单向移动,双向移动,跳跃移动等。如图所示。随机变化。变化花样相同，但节拍及花样的转换都随机出现。二、项目分析这个彩灯控制器其实就是流水灯，根据实验版的具体情况，我打算通过一个花样控制按钮来控制八盏LED小灯按照4种方法循环

2、点亮。并且在LED变换周期上（即分频周期）我打算用一个计数器来实现在分频的同时自动切换0.5秒和0.25秒两种不同频率。三、 设计流程1. 分频器设计在分频器的设计中，我一开始采用了之前课堂上用过的50MHz分频1Hz的分频器进行修改，修改成具有4Hz分频的分频器：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity devide isport(clk :in std_logic;clk_out:out std_logic);end devide;architecture arc_devi

3、de of devide issignal count:std_logic_vector(30 downto 0);beginprocessbeginwait until clk'event and clk='1'if(count<1250000000)thencount<=count+1;clk_out<='0'elsecount<=(others=>'0');clk_out<='1'end if;end process;end architecture arc_devide;之后按我

4、的想法是再额外增设一个计数器来进行切换4Hz和2Hz，但是在仿真的时候出现了严重的毛刺现象，经过信号源修正未果。所以我对设计思路进行了反思，后来发现可以直接吧计数器加到分频器中，这样可以避免毛刺现象，修改后的程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity big isport(clk :in std_logic;clk_out:out std_logic);end big;architecture arc_devide of big issignal count:std_l

5、ogic_vector(30 downto 0);signal coun:std_logic_vector(3 downto 0);beginprocessbeginwait until clk'event and clk='1'if(count<12500000)thencount<=count+1;clk_out<='0'elsecount<=(others=>'0');coun<=coun+1;if(coun<9 or coun=10 or coun=12 or coun=14)thencl

6、k_out<='1'elsif(coun<15)thenclk_out<='0'elseclk_out<='0'coun<=(others=>'0');end if;end if;end process;end architecture arc_devide;我通过定义另一个内部信号coun来实现信号多种分频。为了确认程序的可行性，我将底层频率修改成2Hz进行仿真，得到的结果如下：通过仿真波形可以看出明显的频率变化。2. 花样设计我在这次的流水灯设计中共采取了4种不同的花样。花样一：100000

7、0001000000001000000001000000001000000001000000001000000001library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hua1 is PORT(CLK :IN STD_LOGIC; M :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);end hua1; architecture Behavioral of hua1 is SIGNAL SEL : STD

8、_LOGIC_VECTOR(2 DOWNTO 0); begin PROCESS(CLK,SEL) BEGIN IF RISING_EDGE(CLK) THEN IF SEL="111" THEN SEL<="000" ELSE SEL<=SEL+'1' END IF; END IF; CASE SEL IS WHEN "000" =>M<="10000000" WHEN "001" =>M<="01000000" WHEN

9、 "010" =>M<="00100000" WHEN "011" =>M<="00010000" WHEN "100" =>M<="00001000" WHEN "101" =>M<="00000100" WHEN "110" =>M<="00000010" WHEN "111" =>M<="0

10、0000001" WHEN OTHERS =>NULL; END CASE; END PROCESS; end Behavioral;花样二：1000000001000000001000000001000000001000000001000000001000000001library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity hua2 isPORT(CLK :IN STD_LOGIC;N :OUT STD_LOGIC_V

11、ECTOR(7 DOWNTO 0);end hua2;architecture Behavioral of hua2 isSIGNAL SEL : STD_LOGIC_VECTOR(2 DOWNTO 0);beginPROCESS(CLK,SEL)BEGINIF RISING_EDGE(CLK) THENIF SEL="111" THENSEL<="000"ELSE SEL<=SEL+'1'END IF;END IF;CASE SEL ISWHEN "000" =>N<="000000

12、01"WHEN "001" =>N<="00000010"WHEN "010" =>N<="00000100"WHEN "011" =>N<="00001000"WHEN "100" =>N<="00010000"WHEN "101" =>N<="00100000"WHEN "110" =>N<=

13、"01000000"WHEN "111" =>N<="10000000"WHEN OTHERS =>NULL;END CASE;END PROCESS;end Behavioral;花样三：1000000101000010001001000001100000011000001001000100001010000001library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

14、entity hua3 isPORT(CLK :IN STD_LOGIC;L :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);end hua3;architecture Behavioral of hua3 isSIGNAL SEL : STD_LOGIC_VECTOR(2 DOWNTO 0);beginPROCESS(CLK,SEL)BEGINIF RISING_EDGE(CLK) THENIF SEL="111" THENSEL<="000"ELSE SEL<=SEL+'1'END IF;END IF;

15、CASE SEL ISWHEN "000" =>L<="10000001"WHEN "001" =>L<="01000010"WHEN "010" =>L<="00100100"WHEN "011" =>L<="00011000"WHEN "100" =>L<="00100100"WHEN "101" =>L&l

16、t;="01000010"WHEN "110" =>L<="10000001"WHEN "111" =>L<="00000000"WHEN OTHERS =>NULL;END CASE;END PROCESS;end Behavioral;在这里有必要提一句，由于我的循环方式的各种问题导致产生了一些毛刺，但是在实际调用中，并没有出现过于明显的误差。花样四：10000010010000011010000001010000001010000001010000001010

17、00000101library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity hua4 isPORT(CLK :IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);end hua4;architecture Behavioral of hua4 isSIGNAL SEL : STD_LOGIC_VECTOR(2 DOWNTO 0);beginPROCESS(CLK,SEL)BEGINIF RIS

18、ING_EDGE(CLK) THENIF SEL="111" THENSEL<="000"ELSE SEL<=SEL+'1'END IF;END IF;CASE SEL ISWHEN "000" => Q <="10100000"WHEN "001" => Q <="01010000"WHEN "010" => Q <="00101000"WHEN "011&qu

19、ot; => Q <="00010100"WHEN "100" => Q <="00001010"WHEN "101" => Q <="00000101"WHEN "110" => Q <="10000010"WHEN "111" => Q <="01000001"WHEN OTHERS =>NULL;END CASE;END PROCESS;end

20、Behavioral;3. 花样切换花样切换方式我选择的是通过一个botton的上升沿运动推动计数来实现花样切换。因为我的设计中有四种花样，所以我就选择了一个4模计数器来实现这个功能。library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xuan is port( xuan:out std_logic_vector(1 downto 0); sel:in std_logic); end xuan; architecture fun of xuan is signal count:std_logic_vector(1 downto 0); begin processbeginwait until sel'event and sel='1'if(count<3)thencount<=count+1;elsecount<=(others=>'0');end if;xuan<=count;end process; end fun;4顶层设计顶层设计我选择设计一个4