内容提要_20-13

1、VHDL 3BASIC OPERATORS AND ARCHITECTURE BODYDesign descriptions & Design constructions examples are taken from foundation series examplesexercise 3: VHDL(v.2b)1化妆品 http:/We will learnOperators andDifferent architecture design methods1) Structural2) Data flow3) BehavioralUse of signals and variabl

2、esexercise 3: VHDL(v.2b)2VHDL OPERATORSAnd their usageexercise 3: VHDL(v.2b)3Typical Operators exercise 3: VHDL(v.2b)4Logical / relation operatorsAnd, or, nand, nor, xor, xnor, not - have their usual meanings. But nand is not associative :A nand B nand C is illegal. Exercise 3.1: Draw the truth tabl

3、e to show (A nand B) nand C A nand (B nand C)Relation operators= equal ; /= not equal = smaller, bigger , equal etc.exercise 3: VHDL(v.2b)5Exercise 3.1: Fill in “?_”.It shows the NAND-gate is not associative , so A nand B nand C is illegal. (A nand B) nand C A nand (B nand C)A B CA nand B(A nand B)

4、nand CB nand CA nand (B nand C)0 0 0 11110 0 1 1?_110 1 0 11110 1 1 10?_11 0 0 11101 0 1 101?_1 1 0 01101 1 1 01?_1exercise 3: VHDL(v.2b)6Student ID: _Name: _Date:_ (Submit this at the end of the lecture.)Shift operatorssee VHDL for Engineers (Google books) Kenneth L. Short - 2008 - Computers - 685L

5、ogical shift and rotateSll (shift left logical, fill blank with 0); srl (shift right logical, fill blank with 0)rol(rotate left logical ); ror(rotate right logical) circular operation.E.g. “10010101” rol 3 is “10101100”Arithmetic shift (/wiki/Arithmetic_shift)sla (shift left ar

6、ithmetic) fill blank with 0,same as sll (shift left logical)sra (shift right arithmetic), fill blank with sign bit (MSB)exercise 3: VHDL(v.2b)7Exercise 3.2 on shift and rotateA = “10010101”;A sll 2 =_A srl 3 =_A sla 3 =_A sra 2 =_A rol 3=_A ror 5 =_exercise 3: VHDL(v.2b)8Some basic operators+ arithm

7、etic add, for integer, float.- arithmetic subtract, for integer, float.& concatenation: 0 & 1 is “01”, Notice the use of “&”.exercise 3: VHDL(v.2b)9Some basic operators* multiplication / divisionmod =modulus=E.g. A mod B= A-(B*N) - N is an integerabs = absolute value* = exponentiationexe

8、rcise 3: VHDL(v.2b)10ARCHITECTURE BODYDesign methodsexercise 3: VHDL(v.2b)113 types of design descriptionexercise 3: VHDL(v.2b)121. Structural(parallel)2. Data Flow(parallel)3. Behavioral(serial)Designdescription(1) Structural design description methodexercise 3: VHDL(v.2b)131. Structural(parallel)2

9、. Data Flow(parallel)3. Behavioral(serial)DesigndescriptionStructural :Like a circuit but describe it by text. exercise 3: VHDL(v.2b)14Component AComponent BComponent CRelated by port map in architectureStructural :Like a circuit but describe it by text.Step1: Create entitiesStep2: create components

10、 from entitiesStep3: create “port map” to relate the componentsexercise 3: VHDL(v.2b)15Step1 of Structural DescriptionCreate the and2 chip :an entity and21 entity and2 is port (a,b : in std_logic;2 c : out std_logic);3 end and24 architecture and2_arch of and25 begin6 c =a and b;7 end and2_archexerci

11、se 3: VHDL(v.2b)16Step 2 : Create component “and2” based on “entity and2”10 component and211 port (a,b: in std_logic; c out std_logic); 12- note sequence of a,b,c13 end component14 - now use it in “port map” instructionsexercise 3: VHDL(v.2b)17Component “and2”a = inputc= outputb = inputStep 3 : conn

12、ect components using port map-assume and2 , or2 are user defined components21 architecture struct_abc of abcx is22 begin23 label_u0:or2 port map (a, b, x);24 label_u1:and2 port map (c,x,y);25 end struct_abc;26 -label_u0 ,label_u1 are line labels.exercise 3: VHDL(v.2b)18acxybWhat will happen if these

13、 2 lines are interchanged ?Core of the structural design21 architecture struct_abc of abcx is22 begin23 label_u1:and2 port map (c,x,y);24label_u0:or2 port map (a, b, x);25 end struct_abc;exercise 3: VHDL(v.2b)19Label_u0,label_u1 are line labels“port map” are reserved wordsacxyblines can be interchan

14、gedExercise: 3.3:(a) When will line 23 and 24 be executed? Answer: _(b) Draw the schematic diagram if a VHDL program has lines23 label_u0:and2 port map (a, c, x);24 label_u1:or2 port map (b,x,y);(c) Complete line 23 and 24 if the circuit is 23 label_u0: ?_24 label_u1:?_exercise 3: VHDL(v.2b)20acxyb

15、entity test_andor2 is - A detailed example port ( in1: in STD_LOGIC; in2: in STD_LOGIC; in3: in STD_LOGIC; out1: out STD_LOGIC ); end test_andor2;architecture test_andor2_arch of test_andor2 iscomponent and2 port (a,b:in std_logic; c: out std_logic); end component ;component or2 port (a,b:in std_log

16、ic; c: out std_logic); end component ;signal con1_signal: std_logic;begin label1: and2 port map (in1, in2, con1_signal); label2: or2 port map (con1_signal, in3, out1);end test_andor2_arch;exercise 3: VHDL(v.2b)21in1in3out1in2Con1_signal Exercise 3.4Draw the schematic diagram of the half-adder based

17、on architecture struct_abc entity half_adder is - another example port ( a: in bit; b: in bit; sum: out bit; carry: out bit );end half_adder;architecture half_adder_arch of half_adder iscomponent xor2 port(x,y: in bit; z: out bit);end component;component and2 port( l,m: in bit; n: out bit);end compo

18、nent;begin label1: xor2 port map (a,b,sum); label2: and2 port map (a,b, carry);end half_adder_arch;exercise 3: VHDL(v.2b)22(2) Data flow design description methodexercise 3: VHDL(v.2b)231. Structural(parallel)2. Data Flow(parallel)3. Behavioral(serial)DesigndescriptionData flow: concurrent execution

19、1 entity eqb_comp4 is2 port (a, b: in std_logic_vector(3 downto 0);3equals,bigger:out std_logic);4 end eqb_comp4;5 architecture dataflow4 of eqb_comp4 is6 begin7 equals = 1 when (a = b) else 0 ;-concurrent8 bigger b) else 0;-concurrent10 end dataflow4;exercise 3: VHDL(v.2b)24Exercise: 3.5: Exercise

20、based on entity eqb_comp4 1 entity eqb_comp4 is2 port (a, b: in std_logic_vector(3 downto 0);3equals,bigger: out std_logic);4 end eqb_comp4;5 architecture dataflow4 of eqb_comp4 is6 begin7 equals = 1 when (a = b) else 0 ;-concurrent8 bigger b) else 0;-concurrent10 end dataflow4;(a) When will lines 7

21、, 8 be executed?Answer: _exercise 3: VHDL(v.2b)25Exercise3.6 : Draw the schematic of this codeEntity abc isPort (a,b,c: in std_logic;y out std_l;ogic);end abc;Architecture abc_arch of abc issignal x : std_logic;Begin x= a nor b; y =x and c;end abc_arch;exercise 3: VHDL(v.2b)26(3) Behavioral design d

22、escription method Using Process( ) exercise 3: VHDL(v.2b)271. Structural(parallel)2. Data Flow(parallel)3. Behavioral(serial)DesigndescriptionBehavioral design is sequentialthe keyword is processSequential, inside a processJust like a sequential programthe main character is process(sensitivity list)

23、exercise 3: VHDL(v.2b)28 1 entity eqcomp4 is port(2a, b:in std_logic_vector(3 downto 0);3equals: out std_logic);4 end eqcomp4;5 architecture behavioral of eqcomp4 is6 begin7 comp: process (a, b)8begin9if a = b then10equals = 1;11else12equals = 0;13end if;14end process;15 end behavioral;exercise 3: V

24、HDL(v.2b)29Behavioral design:It is sequential,the keyword is processsequential executionlike a sequential software programExercise 3.7: Exercise based on eqcomp4 (a) When will line 7, the process( ), be executed?Answer:_(b) When will line 9,10 be executed?Answer:_1 entity eqcomp4 is port(2 a, b:in s

25、td_logic_vector(3 downto 0);3equals: out std_logic);4 end eqcomp4;5 architecture behavioral of eqcomp4 is6 begin7 comp: process (a, b)8 begin9if a = b then10 equals = 1;11 else12 equals = 0;13 end if;14end process;15 end behavioral;exercise 3: VHDL(v.2b)30Concurrent VS sequentialEvery statement insi

26、de the architecture body is executed concurrently, except statements enclosed by a process.ProcessStatements within a process are executed sequentially. Result is known when the whole process is complete.You may treat a process as one concurrent statement in the architecture body.Process(sensitivity

27、 list): when one or more signals in the sensitivity list change state, the process executes once.exercise 3: VHDL(v.2b)31DESIGN CONSTRUCTIONSConcurrent and sequentialexercise 3: VHDL(v.2b)32Design constructionsConcurrent: statements that can be stand-aloneWhen-elseWith-select-whenSequential: stateme

28、nts that can only live inside processesCase-when forin-to-loopIf-then-elseexercise 3: VHDL(v.2b)33sequential - with processesConcurrent sequential - NO processDesign constructions Concurrent statementsDesign constructionsConcurrentstand-alone(No process)Sequentialstatements live in processes( )when

29、elsewith select whenCase-when for-in-to-loopif-then-elseexercise 3: VHDL(v.2b)34Concurrent: statements that can stand-alone(concurrent 1) when-else(concurrent 2) with-select-whenexercise 3: VHDL(v.2b)35When-else : example and-gate1 entity when_ex is2 port (in1, in2 : in std_logic;3 out1 : out std_lo

30、gic);4 end when_ex;56 architecture when_ex_a of when_ex is7 begin8 out1 = 1 when in1 = 1 and in2 = 1 else 0;9 end when_ex_a;exercise 3: VHDL(v.2b)36And-gatein1in2outWith-select-when : example and-gate again1 entity with_ex is 2 port (in1, in2 : in std_logic; 3 out1 : out std_logic);4 end with_ex;5 a

31、rchitecture with_ex_a of with_ex is6 begin7 with in1 select8 out1 = in2 when 1,-means when in1=19 0 when others;-other cases10 end with_ex_a;exercise 3: VHDL(v.2b)37And-gatein1in2outDesign constructions Sequential statementsDesign constructionsConcurrentstand-alone(No process)Sequentialstatements li

32、ve in processes( )when elsewith select whenCase-when for-in-to-loopif-then-elseexercise 3: VHDL(v.2b)38Process( sensitivity list of signals) for sequential execution1 architecture for_ex_arch of for_ex is2 begin3 process (in1, in2) - execute once when the signals 4 -in the sensitivity list (I.e. in1

33、 or in2) change state5 begin6 out1 = in1 and in2;7 :8 end process;9 out2 out1 = 0; 8 out2 out1 = 1; 10 out2 = 0; 11 end case; 12 end process; 13 b ” means “implies” not “bigger”all cases must be present, use others to complete all casesans:exercise 3: VHDL(v.2b)42b(0)b(1)out1out2Ex-norFor-in-to-loop

34、 (example invert 4 inputs)1 architecture for_ex_arch of for_ex is2 begin3 process (in1)4 begin5 label_for0 : for i in 0 to 3 loop6 out1 (i) = not in1(i);7 end loop;8 end process;9 end for_ex_arch;exercise 3: VHDL(v.2b)43in(3:0)out(3:0)Exercise 3.9 : use of FOR Rewrite arch1 without a process( ).1 ar

35、chitecture arch1 of ex1 is 2 begin3456789 end for_ex_arch; 1 architecture arch1 of ex1 is 2 begin3 process (in1)4 begin5 lab0 : for i in 0 to 3 loop6 out1 (i) = not in1(i);7 end loop;8 end process;9 end for_ex_arch;exercise 3: VHDL(v.2b)44 ?If-then-else:example and1 architecture if_ex_a of if_ex is2begin3 process (in1, in2)4 begin5 if in1 = 1 and in2 = 1 then6 out1 = 1;7 else8 out1