哈工大模拟coms第15章 版图

1、Design of Analog Integrated CircuitsLayout2021-11-172Outline 1. General Layout Considerations 2. Analog Layout Techniques 3. Substrate Coupling 2021-11-17315.1 General Layout Considerations Layout2021-11-17415.2 Analog Layout Techniques 15.2.1 Multifinger TransistorsjswjswPCWNNENCNWENC1) 1()22(21202

2、1-11-175 15.2.2 Symmetry2021-11-176 15.2.2 Symmetry2021-11-177 15.2.2 Symmetry2021-11-178 15.2.3 Reference Distribution2021-11-179 15.2.3 Reference DistributionReduce mismatch2021-11-1710 15.2.4 Passive Devices2021-11-1711 15.2.4 Passive Devices2021-11-1712 15.2.4 Passive DevicesLayerR/W/)TC ppm/C 2

3、5CVCppm/VBCppm/VN+ poly30-8005050P+ poly302005050N+ diff701500500-500P+ diff1001600500-500N-well1000-15002000030000)2()()25(1212121BCCCOVVVBVVVTTRIVVR2021-11-1713 15.2.4 Passive DevicesTypeCapa.aF/mm2VCppm/VTCppm/CGate5300hugebigPoly-poly(option)10001025Metal-metal502030Metal-substrate3040Metal-poly

4、5060Poly-substrate120Junction capacitors1000bigbig2021-11-1714 15.2.4 Passive DevicesSWDP-silicon SubstrateOxideVia2M2M32021-11-1715 15.2.4 Passive DevicesnD: 直径:D Q but fsr as parasitic capacitance between substrate and the spiral increases.A good design usually has D 200 mm2021-11-1716 15.2.5 Inte

5、rconnects2021-11-17172021-11-171815.3. Substrate Coupling Substrate coupling effect2021-11-1719 Methods of minimizing the effect of substrate noise2021-11-1720 Methods of minimizing the effect of substrate noise2021-11-1721 Methods of minimizing the effect of substrate noise2021-11-1722 Methods of minimizing the effect of substrate noise2021-11-1723Summary Layout Techniques Design rules:设计者与fo