EDA程序改错题

1、程序改错题1已知 sei 为 STD_L0GIC_VECT0R(1 DOWNTO类型的信号， 而 a、b、c、d、q 均为 STD_LOGIC 类型的信号，请判断下面给出的CASE语句程序片段：CASE sel ISWHEN“ 00” =>q<=aWHEN“ 01 ” =>q<=bWHEN" 10 ” =>q<；WHEN" 11 ” =>q<=dEND CASE 答案：CASE语句缺“ WHEN OTHER”语句。2已知 data_in1, data_in2 为 STD_LOGIC_VECTOR(1DOWNTO 0)类型的输入

2、端口， data_out 为 STD_LOGIC_VECTOR(15 DOWNTO类型的输出端口， add_sub 为 STD_LOGIC类型的输入端 口，请判断下面给出的程序片段：LIBRARY IEEEENTITY add ISPORT (data_in1, data_in2 : IN INTEGERdata_out : OUT INTEGER;END add;ARCHTECTURE add_arch OF add ISCONSTANT a:INTEGER<=2BEGINdata_out<=( data_in1+ data_in2) * a ;END addsub_arch;答

3、案：常量声明时赋初值的“<=”符号应改用“：='符号。3.已知Q为STD_LOGIC类型的输出端口，请判断下面的程序片段：ARCHITECTURE test_arch OF test ISBEGINSIGNAL B STD_LOGICQ<= B;END test_arch答案：信号SIGNAL的声明语句应该放在 BEGIN语句之前。4.已知A和Q均为BIT类型的信号，请判断下面的程序片段:ARCHITECTURE archtest OF test ISBEGINCASE A ISWHEN ' O' =>Q<= ' 1'WHEN &

4、#39; 1' =>Q<= ' 0'END CASEEND archtest;答案：CASE语句应该存在于进程 PROCESS。三.判断改错题（3分X 6题）（评分标准：给出正确答案 1分/题；答案基本正确0.5分/题。）1. 已知A和Q均为BIT类型的信号，请判断下面的程序片断：ARCHITECTURE test OF test ISBEGINCASE A ISWHEN '0' => Q <= '1'WHEN '1' => Q <= '0'END CASE;END te

5、st ;【参考答案】：CAS语句应该存在于进程PROCES内。2 .已知start为STD_LOGI类型的信号，sum是INTEGER!型的信号，请判断下面的程序片断：PROCESS （start）BEGINFOR i IN 1 TO 9 LOOPsum := sum + i ;END LOOP;END PROCESS【参考答案】：sum是信号，其赋值符号应该由“：=”改为“ <=”。3 .已知Q为STD_LOGI（类型的输出端口，请判断下面的程序片断：ARCHITECTURE test OF test ISBEGINSIGNAL B : STD_LOGIC ;Q <= B ;EN

6、D test ;【参考答案】：信号 SIGNA的申明语句应该放在 BEGIN语句之前。4 .已知A和 B均为STD_LOGI(类型的信号，请判断下面的语句：A <= 'O'B <= 'x'；【参考答案】：不定态符号应该由小写的x'改为大写的 X'。5 .已知A为INTEGERS型的信号，B为STD_LOGI类型的信号，请判断下面的程序片断：ARCHITECTURE test OF test ISBEGINB <= A ;END test ;【参考答案】：A和 B的数据类型不一致，不能相互赋值。6 .已知 sel是STD_LOGI

7、C_VECTOR(1 DOWNTO类型信号，而a、b、c、d、q均为 STD_LOGIC类型信号，请判断下面给出的CASE语句：CASE sel ISWHEN“ 00”=> q <= a ;WHEN“ 01”=> q <= b ;WHEN“10”=> q <= c ;WHEN“11”=> q <= d ;END CASE;【参考答案】： CAS语句缺“ WHEN OTHERS语句。四、判断下面程序中是否有错误，若有错误请改正；1、SIGNAL A,EN:STD_LOGIC; PROCESS(A,EN)VARIABLE B:STD_LOGIC;BE

8、GINIF EN='1 ' THENB<=A;END ;END PROCESS;2、RCHITECTURE ONE OF SAMPLE IS VARIABLE A B, C: INTEGERBEGINC<=A+BEND ;五、判断下列程序是否有错误，如有则指出错误所在(10分)程序：LIBRARY IEEE;ENTITY zyt12 ISPORT(R,EN,CP: IN bit;Q: BUFFER STD_LOGIC_VECTOR(0 DOWNTO 3); CO: OUT STD_LOGIC);END zyt;ARCHITECTURE c10 OF zyt12BEG

9、INCO<='1' WHEN(EN='1' AND Q="1011") ELSE；'0'PROCESS(R,CP)BEGINIF R='1' THENQ<="0000"ELSIF (CP'EVENT AND CP<='1') THENIF EN='0' THENQv=Q;ELSIF Q="1011" THENQ<= '0000'ELSEQ:=Q+1;END IF;END PROCESS;END

10、 one;仔细阅读下列程序，回答问题LIBRARY IEEE;- 1ENTITY LED7SEG IS- 3PORT ( A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);- 4 CLK: IN STD_LOGIC; - 5LED7S: OUT STD_LOGIC_VECTOR(6 DOWNTO 0)- 6END LED7SEG; - 7ARCHITECTURE one OF LED7SEG IS - 8SIGNAL TMP : STD_LOGIC; - 9BEGIN- 10SYNC : PROCESS(CLK, A) - 11BEGIN - 12IF CLK'EV

11、ENT AND CLK = '1' THEN- 13TMP <= A;- 14END IF; - 15END PROCESS; - 16OUTLED : PROCESS(TMP) - 17BEGIN - 18CASE TMP IS - 19WHEN "0000" => LED7S <= "0111111"- 20WHEN "0001" => LED7S <= "0000110"- 21WHEN "0010" => LED7S <= &qu

12、ot;1011011"- 22WHEN "0011" => LED7S <= "1001111"- 23WHEN "0100" => LED7S <= "1100110" - 24WHEN "0101" => LED7S <= "1101101" - 25WHEN "0110" => LED7S <= "1111101"- 26WHEN "0111" =>

13、; LED7S <= "0000111"- 27WHEN "1000" => LED7S <= "1111111"- 28WHEN "1001" => LED7S <= "1101111"- 29END CASE;- 30END PROCESS; - 31END one; - 321. 在程序中存在两处错误，试指出，并说明理由： 第14行TMP附值错误第29与30行之间，缺少 WHEN OTHER需句2. 修改相应行的程序：错误1 行号：9程序改为：TMP : ST

14、D_LOGIC_VECTOR(3 DOWNTO 0); 错误2 行号：29程序改为： 该语句后添加 WHEN OTHERS => LED7S <= "00000001、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ULENTITY T4B ISPORT (CL, RST ENA: IN STD_LOGIC;OUTY : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT : OUT STD_LOGIC );END T4B;ARCHITECTURE behav OF T4B ISSIGNAL CQI : STD_LOGIC

15、_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK, RST, ENA)BEGINIF RST = '1' THEN CQI <= '0000':"0000"ELSIF CLK'EVENT AND CLK = '1' THENIF ENA =_"1" THEN CQI <= CQI + 1;'1'ELSE CQI <= "0000"END IF;END IF;OUTY <= CQEND PROCESS;COUT<

16、=CQI(0) AND CQI(1) AND CQI(2) AND CQI(3);END behav;2、LIBRARY IEEE;USE IEEE.STD_LOGIC_ARITH.ENTITY CLK_6D ISPORT (CLK,RST: IN STD_LOGIC;CLK_OUT: OUT STD_LOGIC);END CLK_6D;ARCHITECTURE ONE OF CLK_6D ISVARIABLE TEMP:STD_SJO3GIA；LBEGINPROCESS(CLK)VARIABLE T6D: INTEGER RANGE 0 TO 3;CONSTANT SIGN: INTEGER

17、:=2;BEGINIF (RST “ 1 ”)THEN TEMP <“0” ;'1' , 'O'ELSIF CLK'EVENT AND CLK二'1' THEN (CLK'EVENT AND CLK='1')IF (T6D = SIGN) THEN T6D := 0;TEMP <= NOT TEMP;ELSE T6D := T6D+1; END IF;END IF;END PROCESSLK_OUT <= TEMP;END ONE;3、library ieee;en tity en coder i

18、sport(b_ in std_logic(7 dow nto 0);b:in std_logic_vector(7 dow nto 0) 乂 out stdo gic(2 dow nto 0); y:out stdo gic_vector(2 dow nto 0) end en coder;architecture one of en coder is beg in process (b)beg incase b iswhen "01111111"=>y<="111"when "10111111"=>y<=&

19、quot;110"when "11011111"=>y<="101"when "11101111"=>y<="100"when "11110111"=>y<="011"when "11111011"=>y<="010"when "11111101"=>y<="001"when "iiiiiiiO"=>y

20、v="OOO"； when others => null;end casee nd process;end one;4、LIBRARY IEEE;ENTITY cou nter ISPORT ( reset: IN STD_LOGIC; clock: IN STD_LOGIC;num: buffer in teger range 0 to 3 ； 多一个“；”);END;ARCHITECTURE behav OF jish|isSu 改为 coun ter Beg inProcess(reset,clock)Beg inIf reset=' 1' th

21、ennum<=0;Elsif ris in g_edge(clock) the nIf num=3 the nnum<=0;elsenum<=num+1;少 end if;end if;end process;end;5、LIBRARY IEEE;USE IEEE.STD LOGIC UNSIGNED; STD_LOGIC_UNSIGNED.ALLENTITY LX3_2 ISPORT(CLK,CLR,OE:IN BIT;D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END LX3_2;ARCHITECTURE struc OF LX3_2 ISVARIABLE Q_TEMP:STD_LOGIC_VECTOR(7DOWNTO 0); SIGNALBEGIN PROCESS(CPROCESS(CLK)BEGINIF CLR='0' THEN Q TEMP<='00000000'"00000000"ELSIF CLK='1' T