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1、Molded Underfill (MUF Technology for Flip Chip Packages in Mobile Applications Joshi M., Pendse R., Pandey V., Lee T.K., Yoon I.S., Yun J.S., Kim Y.C., Lee H.R.,STATS ChipPAC Inc.AbstractIncreased functionality requirements coupled with progressively reducing package size have necessitated the integ

2、ration of flip chip packages into various baseband and application processor products in mobile platforms. Such products use flip chip technology using traditional capillary underfill (CUF process on a strip based package which is subsequently over molded to finish the end-product assembly. The grow

3、ing pricing pressures and competitive landscape in mobile-packaging has made it imperative for assembly subcontractors to drive the flip chip assembly cost down. To achieve this without compromising product reliability requires a fundamental shift in the way these packages are assembled. Molded unde

4、rfill (MUF approach offers such unique solution with promising advantages over CUF; such as lower material cost, higher through put and excellent reliability to meet the overall product needs of todays evolving mobile market; and is discussed in this paper.Capillary Underfill (CUF has been the corne

5、rstone of todays flip chip technology in both flip chip BGA and flip chip CSP format. Several advancements in CUF materials and dispense technologies made over years has made CUF the underfill technology of choice for various flip chip applications. However as the need for reducing package assembly

6、cost has grown simultaneously; CUF material and underfill process comes under scrutiny due to higher material cost and slow through put process in the flip chip assembly flow. MUF was explored and found to be a viable lower cost alternative for mobile products by virtue of lower material cost and fa

7、ster throughput due to batch process operation in strip format. The cost benefit is further complemented by the capability of MUF to enable finer spacing between die-to-die and die-to-passives; as well as smaller keep-out zones to enable reduced die-to-package edge clearance or effectively shrink th

8、e overall package size than that with CUF. Use of vacuum assisted molding was also found to be capable to fill very small gap between die and substrate of the order of 50um without voiding concerns.This paper outlines the multidisciplinary effort undertaken to design, develop, and qualify flip chip

9、package with MUF technology for mobile application; which was successfully introduced in high volume production with yields and reliability at parity with an equivalent CUF package. MUF material with fine filler size was chosen from a material screening DOE; and was used in series of test vehicles (

10、TVs with different package configurations including single die and multi-die flip chip CSP packages. Process and material margin studies were conducted to establish process window for MUF technology with eutectic and Pb-free bump assemblies. Finally MUF technology was intercepted on mobile applicati

11、on processor product with fcTFBGA-12x12 mm sq. package and 7.5X7.5 mm2 die towards a successful introduction into high volume production. MUF challenges as well as known-limitations are also described along with future plan. Further studies are being conducted to characterize and qualify MUF on larg

12、er die sizes and/or with finer bump pitches and to establish the process and reliability margins of MUF with the same.1.IntroductionMUF is inherently conducive process for mobile products as they are often made in CSP format using strip type substrates which can be molded using traditional mold syst

13、ems. Conventional flip chip CSP used in mobile products use 2 step approach; first using capillary underfill process to underfill the gap between die and package substrate using underfill material; and second using standard mold compound to over mold the package. Mold Underfill (MUF assembly concept

14、 uses a single step approach to both underfill and over mold the die during the same mold shot thus making the process lot simpler and faster than that with CUF. The schematic exemplifying this primary process difference between the two is shown in Figure 1.1 below.Figure 1.1 Comparative Package Sch

15、ematic Illustration of Capillary Underfill and Mold Underfill.Despite continued improvements in both the material properties as well as dispensing systems and mechanisms; underfill process still remains as one of the slowest processes in flip chip assembly flow. This is primarily due to the fact tha

16、t it is not a batch process and needs to be done in a unit-by-unit manner with typically up to two dispense heads used in tandem to complete underfilling of multiple units on a boat or in a strip. Secondly; capillary flow of underfill being surface tension driven flow; is also slow being dependent o

17、n multiple factors; including the solder mask and die passivation material types; die size, bump count and pitch, etc.; which adds to the total underfilling time.MUF on the other hand can be done as a batch process molding the entire strip with much faster throughput. Using vacuum assisted mold syst

18、em with fine fillers MUF materials; very small gaps under the die or passives; as well as narrow spaces between the two die or passives on the package can be filled without concerns of voids.Usually highly filled mold materials with relatively finer filler sizes than those used in over mold compound

19、s are used for MUF materials. Higher filler loading helps with lowering the CTE of the material; required to minimize the CTE mismatch between Silicon die-MUF material-and package substrate. Figure 1.2 shows the filler distribution of MUF mold compound filling gap under the flip chip die.2 step proc

20、ess (Underfill + Mold Single Step Process (Mold Underfill CUF MUFCBFillA Figure 1.2 Cross-sectional View of flip Chip with MUF By choosing material with finer filler size and optimizing vacuum mold process for the same; very small gaps of the order of 50um can also be filled without trapping any mol

21、d void as shown in Figure 1.3. Figure 1.3 Cross-sectional View of Chip Capacitor with 50um gap Filled with MUF Material.2. Package Design Consideration with MUFMUF poses some key advantages over CUF when it comes to designing a flip chip package for a mobile product. CUF approach; using capillary di

22、spense method forms fillets around the die along all four sides. The underfill fillet at the dispense side usually has the largest width. Hence the package designers are required to keep minimum clearances between die edge to package edge as well as between two die or die and a neighboring passive c

23、omponent in case of a SiP to fit in the underfill fillet.MUF; due to its unique vacuum mold process unlike the CUF; does not require underfill fillets; allowing the designers to keep the die and/or the components much closer to each other; thus offering the following benefits i Allowing package desi

24、gners to keep smallerkeep-outs and enabling a smaller package size with lower package / substrate cost;ii Save real estate on PCB with smaller resultingpackages with MUF;iii Improved electrical performance with lowerinductance path between a capacitor and power bumps on the die.Figure 2.1, Figure 2.

25、2, and Table 2.1 illustrate production compatible package design rules comparison for flip chip CSP using MUF vs. CUF.AUF dis p ensin gsideBCFigure 2.1 Package Design Rules with Clearance Requirements for flip chip SiP with CUF.BACFigure 2.2 Package Design Rules with Clearance Requirements for flip

26、chip SiP with MUF.CUF MUFA Pkg edge to die edge0.4mm - 1.3 mm 0.1mm -0.2mm B Clearance btw dies0.8mm -1.0 mm0.3mm -0.4mmC Bump standoff height30um-50um 45um-60um Design RulesCUF and MUF.Evolving requirements for mobile products demanding smaller, faster and cheaper packages have put the overall manu

27、facturing of the packages under scrutiny and the design benefits offered by MUF have caught the eyes of product designers and package assemblers alike.3. MUF MaterialsMold materials used as over mold compounds in wire bonded or flip chip CSP devices are ubiquitous in mobile packages of today. Their

28、manufacturability as well as reliability has been proven through field applications over several years. However the mold materials intended for use as MUF have not been as common to date; as they are subjected to more stringent requirements than typical over mold materials. MUF materials need to flo

29、w under flip chip die in small stand off heights and in between hundreds to thousands of bumps with a range of bump pitches. Generally flip chip bump gap with substrates using Solder on Pad (SOP is <80 um; and with Non-SOP (nSOP assemblies could go down to <50um range. Bump pitches for mobile

30、products tend to be with-in a range of 150um to 180u as of today; but shrinking rapidly for majority of the products. Hence MUF material needs to be capable to fill in such fine gaps without trapping voids under the flip chip die which otherwise could result in assembly yield loss or worse; a latent

31、 failure during board assembly or in the field.Other key requirement posed on MUF material is its coefficient of thermal expansion (CTE; which needs to be lowered to similar levels as capillary underfill to be able to minimize CTE mismatch between silicon and substrate. Hence MUF materials are very

32、highly filled; which helps to reduce the CTE but makes the mold flow more difficult. To fulfill these two contradictory requirements posed on MUF; afiner filler size is chosen along with vacuum assisted molding to help with the mold flow yet keeping the higher filler loading to maintain the low CTE.

33、 Figure 3.1 shows material property chart showing a generic range of mold material properties which MUF material is selected from. The range of filler % content and Tg used to choose MUF materials from is shown with a rectangular box. MUF Range Figure 3.1 MUF Material Properties.Effect of filler siz

34、e in MUF on voiding performance wastested using fcVFBGA-SS3 (3-die side-by-side, 9.0 X 9.0mm Test vehicle with 200u minimum bump pitch and using four separate MUF materials with range of different filler sizes from high to low. Impact of stand-off height was also studied using substrates w/ Cu-OSP (

35、no SOP finish and with SOP finish. Only the MUF materials with finer (medium-to-Low resulted into void-free assembly with both Severe mold voids were encountered with material M1 with High filler sizes with both substrate sources. X-section analysis revealed that mold flow with High filler sized MUF

36、 material (M1 under small gap causes uneven filler distribution; which might have caused the mold voids to form. Figure 3.2 shows the filler distribution comparison between units assembled using M1 (High filler size vs. M4 (Low filler size MUF materials M4-Filler size - LowM4-Filler size - HighFigur

37、e 3.2 X-Section Analysis of Unit Assembled with M1 and M4 MUF materials.Another consideration when choosing the MUF materials is its working temperature range. Typically very high mold temperatures are required to allow good mold flow of MUF materials. Which could be in the close vicinity of the mel

38、ting temperature of eutectic bump (183 °C. Hence it is preferred to use a material with wide working temperature range and that can be molded at as much lower temperature than 183 °C as possible to avoid melting the bump during mold process which could otherwise could cause the device chip

39、 to de-wet from the package substrate during molding process.A controlled experiment was run to find a safe working temperature range of the chosen MUF material for subsequent studies. A temperature-viscosity characteristic chart provided by the MUF material supplier as shown in Figure 3.3 was used

40、to define the working range of chosen MUF materials for evaluation purpose.Figure 3.3 Viscosity vs. Mold Temperature Characteristic of MUF material.The experiment was run using fcVFBGA 12x12 mm2 packages with single flip chip die using eutectic bumps. DOE with 7 different legs with mold temperatures

41、 ranging from high to low were run. Through scan after mold was used as response variable to judge the molding process robustness w.r.t. mold temperatures.All mold temperatures except High temperature showed no particular issues with mold flow, or mold voids. However severe chip-flying accompanied b

42、y mold delamination (from substrate was observed at high mold temperature as shown in Figure 3.4. The phenomenon was found to be caused due to mold temperatures during MUF process reaching close to eutectic melting point.(High (Medium Low Mold TemperatureFigure 3.4 Flip Chip Solder De-wetting at Hig

43、h Mold Temperature.Based on those results, a medium molding temperature condition with adequate temperature tolerance on either ends was established as optimal mold temperature range for flip chip assemblies with eutectic bump using the chosen MUF material.Another key material property of MUF materi

44、al is its Spiral Flow property which represents flowability of mold material under controlled conditions of pressure and temperature, along a spiral runner of constant cross section. Its measured in terms of distance units that mold materials travels. The mold material of choice needs to be tested f

45、or its flow over the specification range of spiral flow due to possible variations from different material batches.A controlled study was run to check the spiral flow specification range of the chosen MUF material through assembly and temperature-humidity testing. Table 3.2 summarizes the results of

46、 the Spiral flow study experiment conducted using the MUF material of choice showing no voids or reliability concerns within the specification range. MUF material batches with target-Nominal spiral flow as well as those towards upper (USL and lower (LSL end of the specification were tested and found

47、 to be robust in terms of mold flow under the die confirming no voids; as well as reliability through temperature-humidity testing.4.Assembly Process for MUFMUF package assembly process flow is much simpler than the conventional - (underfill + over mold process flow as MUF material accomplishes unde

48、rfilling and over molding functions in single step; thus eliminating pre-underfill plasma, underfill, and underfill cure processes; making the overall assembly process time much faster.Figure 4.1 shows process flow used for MUF assembly of flip chip CSP. Figure 4.1 MUF Process Flow for Flip Chip CSP

49、.However optimizing the process parameters for MUF is a non-trivial task requiring extensive characterization of each critical assembly process step; to ensure robustness across the process window. A comprehensive effort was undertaken to check the robustness of the selected MUF material before high

50、 volume production ramp. Mold parameters, and process window times were studied as the key factors of MUF process; besides the MUF material properties as described in Section 3 of this paper.MUF Process Parameter StudyA Process FMEA (pFMEA was conducted to identify key processes to study to establis

51、h a robust operating window for each. Amongst the mold parameters; mold transfer pressure, mold transfer time and preheat time were chosen to check the robustness of the chosen MUF material within the operating window of each key parameter. MUF voids using through scan (T SAM and temperature-humidit

52、y testing were used as response variables to ensure no voids and mold delamination respectively.Effect of Pre-Bake Window TimePre-bake step is done as a default before molding process to ensure moisture is removed; but the process window time between pre-bake-out to mold process needs to be controll

53、ed as well to ensure effectiveness of the pre-bake process. Hence studies to establish process window margin were run with different window times in a separate study. Impact of these process window times (i.e. moisture absorbed during pre-bake and mold on MUF void performance was checked. Table 4.1

54、summarizes the results obtained with process window study run to assess impact of window times within a range of 24hrs to 60hrs along with different deflux conditions (with (A and without (B saponifier as below. As seen from the results; 24hrs and 48hrs window time showed no mold void, however 60hrs

55、 window time leg resulted in a mold void on one unit. Figure 4-2 shows theTSAM image of mold void trapped near the center of the die; and parallel-lap analysis reveled the void without presence of any contaminant indicating potential moisture induced void due to extended prebake window time of 60hrs

56、. P-Lap of Mold Void Figure 4.2 TSAM and P-Lap of Mold void.Package Warpage with MUF Package warpage is another major consideration for mobile packages to allow card attach assembly with very fine BGA pitches of the order of 0.4mm. Warpage over the reflow range is also critical to manage stress of s

57、ilicon inner layers and low-k as well as on substrate features. Hence its imperative to assess impact of MUF on package warpage to ensure compliance with maximum warpage criteria set by the end-product user. Package coplanarity analysis using RVSI technique was conducted on flip chip FBGA with MUF u

58、sing 12x12 mm 2-package size with 65N-low K fab node Silicon die of 7.5 X 7.5 mm 2 size with eutectic bump. Figure 4.3 shows 3D warpage plot and warpage readings obtained ensuring compliance to the end-customers warpage specification of max. (80u. Chip Package with MUF.Shadow Moiré analysis was

59、 also conducted to check warpage behavior change over the reflow temperature range to sight any abnormal change in warpage with MUF and was confirmed to be a non-issue. Figure 4.4 shows Shadow Moiré warpage plots over the reflow temperature range; showing no X-Scale Chip Package with MUF.5. Reliability Testing with MUF Reliability of CUF has been proven through extensive reliability testing through years of develop