数字集成电路设计

1、数字集成电路设计1. 课程情况简介2. 集成电路系统规模3. 数字与模拟集成电路设计4. 你将在这门课上学到什么？5. 从CMOS到系统的综合概述北京市最大的市属211大学全国20所A类微电子学院之一培训集成电路设计、微电子器件与工艺人才全新的授课内容与理念广阔的就业前景和旺盛的就业需求国际合作与交流将是未来的重要方向微信号：Wensi_Vincent邮箱： 办公室电话： 6739-2620手机： 135209620598次课程：1次介绍课程，7次正式课程周二晚， 9-12节，每次4学时从下次课程起在科学楼（综合楼）中厅考试形式： 40% 平时分（作业、出勤等）+60%考试分参考书目：1. 超

2、大规模集成电路与系统导论 John P. Uyemura 周润德 译2.数字集成电路-设计透视 Jan Rabaey第一次课：历史、发展与宏观概述： “什么是数字微电子”第二次课：MOSFET和CMOS 逻辑门第三次课：CMOS集成电路的物理结构与制造工艺第四次课：Verilog硬件描述语言（常用部件）第五次课：SPICE Level 1&2仿真(以反相器为例）第六次课：版图Layout设计第七次课：系统级物理设计、可靠性与测试第八次课：高速CMOS逻辑与低功率CMOS电路以及内存芯片设计 7n+n+SGD+DEVICECIRCUITGATEMODULESYSTEM8910First tran

3、sistorBell Labs, 194811Bipolar logic1960sECL 3-input GateMotorola 19661219711000 transistors1 MHz operation1315lIn 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. lHe made a prediction that semiconductor technology will double its effectiveness every

4、18 months16171,000,0001,000,000100,000100,00010,00010,0001,0001,00010101001001 119751975 19801980 19851985 19901990 19951995 20002000 20052005 20102010808680868028680286i386i386i486i486PentiumPentium PentiumPentium Pro ProK KPentiumPentium II IIPentiumPentium IIIIIICourtesy, Intel1840044004800880088

5、08080808085808580868086286286386386486486Pentium procPentium procP6P60.0010.0010.010.010.10.11 11010100100100010001970197019801980199019902000200020102010YearYearTransistors (MT)Transistors (MT)2 2X growth in 1.96 years!X growth in 1.96 years!Transistors on Lead Microprocessors double every 2 yearsT

6、ransistors on Lead Microprocessors double every 2 yearsCourtesy, Intel194004400480088008808080808085808580868086286286386386486486Pentium procPentium procP6P61 110101001001970197019801980199019902000200020102010YearYearDie size (mm)Die size (mm)7% 7% growth per yeargrowth per year22X growth in 10 ye

7、arsX growth in 10 yearsDie size grows by 14% to satisfy Moores LawDie size grows by 14% to satisfy Moores LawCourtesy, Intel20P6P6Pentium procPentium proc48648638638628628680868086808580858080808080088008400440040.10.11 110101001001000100010000100001970197019801980199019902000200020102010YearYearFre

8、quency (Mhz)Frequency (Mhz)Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 yearsDoubles every2 yearsCourtesy, Intel21P6P6Pentium procPentium proc48648638638628628680868086808580858080808080088008400440040.10.11 11010100100197119711974197419781978198

9、519851992199220002000YearYearPower (Watts)Power (Watts)Lead Microprocessors power continues to increaseLead Microprocessors power continues to increaseCourtesy, Intel225 5KW KW 1818KW KW 1.51.5KW KW 500500W W 4004400480088008808080808085808580868086286286386386486486Pentium procPentium proc0.10.11 1

10、101010010010001000100001000010000010000019711971 19741974 19781978 19851985 19921992 20002000 20042004 20082008YearYearPower (Watts)Power (Watts)Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitiveCourtesy, Intel2340044004800880088080808080858085808680

11、86286286386386486486Pentium procPentium procP6P61 110101001001000100010000100001970197019801980199019902000200020202020YearYearPower Density (W/cm2)Power Density (W/cm2)Hot PlateHot PlateNuclearNuclearReactorReactorRocketRocketNozzleNozzlePower density too high to keep junctions at low tempPower den

12、sity too high to keep junctions at low tempCourtesy, Intel24 “Microscopic Problems”Microscopic Problems” Ultra-high speed design Ultra-high speed design Interconnect Interconnect Noise, Crosstalk Noise, Crosstalk Reliability, Manufacturability Reliability, Manufacturability Power Dissipation Power D

13、issipation Clock distribution. Clock distribution.Everything Looks a Little DifferentEverything Looks a Little Different “Macroscopic Issues”Macroscopic Issues” Time-to-Market Time-to-Market Millions of Gates Millions of Gates PredictabilityPredictability etc. etc.and Theres a Lot of Them!and Theres

14、 a Lot of Them!? ?25How to evaluate performance of a digital circuit (gate, block, )? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function26 NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Re

15、current costs silicon processing, packaging, test proportional to volume proportional to chip area27Single dieWaferFrom http:/12” (30cm)非常常见28Fabrication capital cost per transistor (Moores law)29%100per wafer chips ofnumber Totalper wafer chips good of No.Yyield Dieper wafer DiescostWafer cost Diea

16、rea die2diameterwafer area diediameter/2wafer per wafer Dies230area dieareaunit per defects1yield die is approximately 3 4area) (die cost diefnppnBASiO2AlABAlABCross-section of pn -junction in an IC process One-dimensionalrepresentationdiode symboln+n+p-substrateDSGBVGS+-DepletionRegionn-channel00.5

17、11.522.50123456x 10-4VDS (V)ID (A)VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 VResistiveSaturationVDS = VGS - VTtoxn+n+Cross sectionCross sectionLGate oxidexdxdLdPolysilicon gateTop viewTop viewGate-bulkoverlapSourcen+Drainn+Wp-welln-wellp+p-epiSiO2AlCupolyn+SiO2p+gate-oxideTungstenTiSi2oxidationoxidatio

18、nopticalopticalmaskmaskprocessprocessstepstepphotoresist coatingphotoresist coatingphotoresistphotoresistremoval (ashing)removal (ashing)spin, rinse, dryspin, rinse, dryacid etchacid etchphotoresist photoresist stepper exposurestepper exposuredevelopmentdevelopmentTypical operations in a single Typi

19、cal operations in a single photolithographic cycle (from Fullman).photolithographic cycle (from Fullman).Connect in MetalShare power and groundAbut cellsVDDC(a) pul l - d o wn netwo rkSN1SN4SN2SN3DFFADBCDFABCsub-net sDAABCVDDVDDB(c) com p l e t e g ateCell boundaryCell boundaryN WellN WellCell heigh

20、t 12 metal tracksMetal track is approx. 3 + 3Pitch = repetitive distance between objectsCell height is “12 pitch”2Rails 10 InInOutOutV VDDDDGNDGNDA AOutOutV VDDDDGNDGNDB B2-input NAND gateBVDDAtransmittersreceiversschematicsschematicsphysicalphysical422 Phase, with multiple conditional buffered cloc

21、ks 2.8 nF clock load 40 cm final driver widthLocal clocks can be gated “off” to save powerReduced load/skewReduced thermal issuesMultiple clocks complicate race checkingtrise = 0.35nstskew = 50pstcycle= 1.67nsGlobal clock waveformGlobal clock waveformPLL2 phase single wire clock, distributed globally2 distributed driver channels Reduced RC delay/skew Improved thermal distribution 3.75nF clock load 58 cm final driver widthLocal inverters for latchingConditional clocks in caches to reduce powerMore complex race checki