DSPBuilder设计入门PPT课件

1、内容与要点,主要内容： DSP Builder 工具介绍；设计流程；设计规范；模块库；设计实例。 本章要点： DSP Builder 设计流程、规范；Simulink模型仿真；利用MATLAB建模工具和DSP Builder开发环境，认识如何将算法级仿真向硬件模块实现过渡的设计过程。,目录(1),第一节、 DSP Builder概述 DSP Builder概述 DSP Builder特性 DSP Builder设计流程 DSP Builder软件安装 实例,目录(2),第二节、 Altera DSP Builder模块库 AltLab库 算术库 总线控制库 复信号处理库 Rate Change

2、模块库 状态机函数库 存储器(Storage）模块库 MegaCore函数支持 其它库,Implementing DSP Designs in FPGA,Overview,The Programmable Solutions Company,Agenda,Overview Designing with DSP Builder Library Blocks Simulating 第二步进行VHDL的综合；第三步调用Quartus II进行综合；如果目标器件为DSP开发板则可以直接将代码下载到DSP开发板上。 底部的Project Info给出了当前系统的信息；Report File给出了Sign

3、alCompiler转换后的硬件信息。,AltLab HDL SubSystem,Create Hierarchical Design Separate HDL Code for Each Subsystem,AltLab HDL SubSystem (cont.),2、算术库,算术库包括二进制补码有符号算术模块，如乘法器、加法器。有些模块有Use Dedicated Circuitry这一选项，即此类模块可以利用Altera tratixII、Stratix、Stratix GX、CycloneII的模块如DSP模块来实现。,Arithmetic Library,Comparator Div

4、ide Gain Increment Decrement Magnitude Multiply Accumulate Multiply Add Parallel Adder Subtractor Product Sum of Partial Products Integrator Differentiator,Arithmetic Library Multiply Add,Arithmetic LibraryDifferentiator b=y+jY; W = v+jV A = a+bW; B = a-bW A = (x+yv)+YV + j(X+Yv-yV) B = (x-yv)-YV +

5、j(X-Yv+yV),Complex Real-Imag to Complex,X = a + Bj Conjugate: Conjugate(X) = a - Bj Invert: Invert(X) = -a - Bj,X = a + Bj Y = C + Dj Multiply: X * Y = (A*C B*D) + (A*D + BC)j,Gate & Control Library,Case Statement If Statement Logical Bit Operator Logical Bus Operator Single Pulse LUT N-to-1 Multipl

6、exer 1-to-N Demux Decoder Bitwise Logical Bus Operator,Gate & Control LibraryEx: Convolutional Interleaver,5、存储器（Storage）模块库,Storage Library,Delay Down Sampling Dual-port RAM FIFO LFSR Sequence LUT Parallel to Serial Pattern ROM EAB Serial to Parallel Shift Taps Up Sampling,Storage Shift Taps,ROM EA

7、B & Shift Taps BlocksEx: Polyphase Filter,Memory Delay BlockEx: 2D Filter,6、Rate Change模块库(1),该库模块允许控制DSP Builder模块如Delay或Increment Decrement模块的时钟。为保证Simulink和VHDL时钟精度的一致则必须设置Simulink的Solver，参数设置见图： 选择Fixed-step； 选择discrete (no continuous state)； 选择Single Tasking模式,6、Rate Change模块库(2),ClockAltr模块 用于

8、仿真模型中加入新的硬件时钟。 PLL模块 可综合出一个基于某一参考时钟的时钟信号。 Multi-Rate DFF模块 用于采样频率的变化 Tsamp 模块 用于指定内部数据的采样时间。,6、Rate Change模块库(3),Rate Change Multi-Rate DFF,Synchronize data path intersections involving multiple rates,Rate Change Tsamp & PLL BlocksEx: Polyphase Filter,7、SOPC Builder Link（1）,NiosII嵌入式处理器是业界领先的软核高性能、高

9、带宽嵌入式处理器，适合网络、通信核大数据量存储等应用。NiosII嵌入式处理器包括RISC CPU和符合业界标准的Cygnus、Red Hat等的GNUPro软件。 用户可以使用SOPC端口库中的模块搭建用户自定义的逻辑模块，且与SOPC Builder相兼容。SOPC Builder支持两种类种类型的用户逻辑模块： 基于Avalon总线的外设； 基于Nios II算术逻辑单元和用户指令的用户自定义逻辑。,7、SOPC Builder Link（2）,当把模型文件转换为VHDL时，SignalCompiler生成一个class.ptf文件。QuartusII进行综合编译后即可加入SOPC Bu

10、ilder。 下图为DSP Builder & SOPC Builder设计流程。,DSP Builder & SOPC Builder设计流程,SOPC Builder Library DSP Acceleration,Custom Peripheral Interface to Nios Through Avalon Bus Custom Instruction Adds Customized Logic to Nios ALU,What is SOPC Builder?,SOPC Builder LibraryCustom Instruction,Add Custom Instructi

11、on Blocks to Simulink Model,SOPC Builder Library Custom Peripheral,Add Avalon Ports to Simulink Model,SOPC Builder Library Avalon Blocks,SOPC Builder Library Avalon Blocks,8、DSP板模块库,Board Library,9、有限状态机,10、MegaCore 函数支持,Altera 的MegaCore函数在Altera的PLD中已经做了严格的测试和性能优化，所有的MegaCore函数都可以通过Altera的MegaWizar

12、d Plug-In Manager进行参数配置。 OpenCore Plus的评估特点允许用户生成时间有限制的可编程文件，通过这些文件可以进行板级的设计验证，然后再购买MegaCore函数的许可证。 DSP Builder目前有如下的IP核： FIR Compiler； IIR Compiler Reed-Solomon Compiler Viterbi Compiler FFT Compiler NCO Compiler ,Alteras IP Megafunctions,Shrink-Wrapped Functions Customers can Drop into Altera FPGA

13、 Designs Optimized for Altera Architectures Easily Parameterized through MegaWizard Plug-in Manager,Megacore IP in DSP Builder,FIR Compiler,1.Generate Floating-Point Coefficients based on Filter Parameters 2. Scale Coefficients to Fixed-Point Values 3. Select Input/Output Specifications 4. Determine

14、 Filter Architecture 5. Select Output Simulation Files,Numerically Controlled Oscillators (NCO),Purpose To Generate a Discrete-Time, Discrete-Value Waveform Approximating a Continuous Waveform to a Defined Precision Primary Application Area Direct Digital Synthesis (DDS) of Sinusoidal Waveforms - I-

15、Q Modulation - Carrier Recovery - Pilot Generation.,Advanced Features,Black Boxing Modelling Guidelines - Clock Design Rules - Multi-Rate Designs - Data Width Propagation - Automatic Sign Extension - Word Growth,Black-Boxing,What is a “black-box” and why is it used? Module or Group of Blocks Left Un

16、processed by DSP Builder Surrounding Blocks Still Converted to HDL Allows HDL Code to Be Added to Simulink Design Use Blocks, C-Based Model or M-File for Simulink Simulation Output Netlist Includes Port Connections to “Black-Box” “Black-Box” Code is Inserted by Quartus II Uses Altbus Blocks in Block

17、 Box Input Output Mode,Replace With Black Box,Looking Under Black Box,AltBus Black Box Mode,Black Box Input & Output Port Creates Black Box Not Converted to HDL Port Connections Remain,实验四（上）,低通数字滤波器设计、高通数字滤波器,实验四（下）,基于滤波器的DTMF信号检测,本章结束,谢 谢 ！,计算机与信息技术学院,What Is an FPGA?,Field Programmable Gate Array

18、 Device that Has a Regular Architecture (Set of Blocks) that Can Be Programmed for Various Functions “Glue” Logic Customizable Hardware Solution Configurable Processors,The Mathworks Design Environment,Top-Down Design Design & Test System Behavior Early in the Design Process Create Validated Reference Design Detect Design Flaws Early Reduced Design Risk & Cost Reduced Time-to-Market,Design Flow with DSP Builder,(八步法),1、AltLab库(1),AltLab库中的模块用于管理设计层次，并产生用于综合和仿真的RTL级的VHDL表述。,Gate & Control Library,Case Statement If Statement Logical Bit Operator Logi