4 参考资料8 sd卡sdio规范sd card 0

1、SD Card SpecificationSimplified Version of:Part E1Secure Digital Input/Output (SDIO)Card SpecificationVersion 1.00October 2001SD AssociationCopyright 2000, 2001 SD AssociationSDIO Simple Specification Version 1.0DO NOT COPYCopyright SD Association, 2000, 2001Revision HistoryConditions for publicatio

2、nPublisher and Copyright Holder:SD Association719 San Benito St. Suite C Hollister, CA 95023USAPhone: +1 831 636 7322Fax: +1 831 623 2248E-mail: Confidentiality:This document is a simplified version of the original. This version is not required to be treated as confidential and No

3、n Disclosure Agreement with neither the 3C LLC nor the SDA is required.Reproduction in whole or in part is prohibited without prior written permission of SDA.Exemption:None will be liable for any damages from use of this document.Important additional information!The reader is directed to the additio

4、nal information available in section Error! Reference source not found. This information will inform the reader of changes to the SDIO specification proposed for the next revision of this specification that should be considered in the design of any SDIO device.lDateVersionChanges compared to previou

5、s issueOctober, 20011.0Base version initial releaseSDIO Simple Specification Version 1.0DO NOT COPYCopyright SD Association, 2000, 2001Table of Contents1.General Description11.11.2SDIO features1Primary Reference Document12.SDIO Signaling Definition22.12.2SDIO Card Types2SDIO Card modes.22.2

6、.3SPI (Card mandatory support)21-bit SD data transfer mode (Card mandatory support)24-bit SD data transfer mode (mandatory for High-Speed cards, optional for Low-Speed)SDIO Host Modes2Signal Pins3Host Requirements for SDIO33.SDIO Card Initialization43.1Differences in I/O card initializatio

7、n44.Differences with SD Memory Specification4.44.5Unsupported SD Memory commands7Bus Width8Card Detect Resistor8Data Transfer Abort8Changes to SD Memory Fixed Registers.24.5.3OCR Register8CID Register8RCA Register85.New I/O Read/Write Commands95.15.2IO_RW_DIRECT command (CMD52)9IO

8、_RW_EXTENDED command (CMD53)95.2.1CMD53 Data Transfer Format96.SDIO Card Internal OperationOverview10Register Access Time10Interrupts10Suspend/Resume11Read Wait (Optional)11SDIO Fixed Internal Map12Common I/O Area (CIA)12Card Common Control Registers (CCCR)13Function Bas

9、ic Registers (FBR)13Card Information Structure (CIS)13Multiple Function SD Cards13Embedded I/O Code Storage Area (CSA)27.SDIO Interrupts147.1Interrupt Timing.27.1.3SPI and SD 1-bit mode interrupts14SD 4-bit mode14Interrupt Clear Timing148.SDIO Physical Properties158.18.2SDIO S

10、ize15SDIO Card Package159.SDIO Mechanical Extensions169.1 Additional ESD/EMI Ground Point169.2 Extended Case169.3 Write Protect Switch1610.SDIO Power1810.1SDIO Card Initialization Voltage18iSDIO Simple Specification Version 1.0DO NOT COPYCopyright SD Association, 2000, 200110.210.311.A.1B.1C.1SDIO P

11、ower Consumption18SDIO Current18Abbreviations and Terms19SD and SPI Command ListANormative ReferencesCExample SDIO Controller DesignDTable of TablesTable 1 SDIO pin definitions3Table 2 Unsupported SD Memory Commands7Table 3 SDIO exceptions to SD physical section 8.1 requirements15Table 4 SD Mode Com

12、mand ListATable 5 SPI Mode Command ListBTable of FiguresFigure 1 Signal connection to two 4-bit SDIO cards3Figure 2 Card initialization flow in SD mode (SDIO aware host)5Figure 3 Card initialization flow in SPI mode (SDIO aware host)6Figure 4 SDIO Internal Map12Figure 5 SDIO Mechanical Extensions17F

13、igure 6 SDIO Internal State Machine exampleDFigure 7 State Diagram for Bus State MachineDFigure 8 State Diagram for Function State MachineEiiSDIO Simple Specification Version 1.0DO NOT COPYCopyright SD Association, 2000, 20011.General DescriptionThe SDIO (Secure Digital I/O) card is based on and com

14、patible with the SD memory card. This compatibility includes mechanical, electrical, power, signaling and software. The intent of the SDIO card is to provide high-speed data I/O with low power consumption for mobile electronic devices. A primary goal is that an SDIO card inserted into a non-SDIO awa

15、re host will cause no physical damage or disruption of that device or its software. In this case, the SDIO card should simply be ignored. Once inserted into an SDIO aware host, the detection of the card will be via the normal means described in the SD specification with some extensions. In this stat

16、e, the SDIO card will be idle and draw a small amount of power (15 mA averaged over 1 second). During the normal initialization and interrogation of the card by the host, the card will identify itself as an SDIO device. The host software will then obtain the card information in a tuple (linked list)

17、 format and determine if that cards I/O function(s) are acceptable to activate. This decision will be based on such parameters as power requirements or the availability of appropriate software drivers. If the card is acceptable, it will be allowed to power up fully and start the I/O function(s) buil

18、t into it.1.1 SDIO features Targeted for portable and stationary applications Minimal or no modification to SD Physical bus is required Minimal change to memory driver software Extended physical form factor available for specialized applications Plug and play (PnP) support Multi-function support inc

19、luding multiple I/O and combined I/O and memory Up to 7 I/O functions plus one memory supported on one card. Allows card to interrupt host Initialization Voltage: 2.0 to 3.6V Operational Voltage range: 3.1 to 3.5V1.2Primary Reference DocumentThis spec is based on and refers extensively to the SDA do

20、cument:SD Memory Card Specifications Part 1PHYSICAL LAYER SPECIFICATIONSeptember 2000Version 1.01The reader is directed to this document for more information on the basic operation of SD devices. In addition, other documents are referenced in this specification. A complete list can be found in secti

21、on B.1.1SDIO Simple Specification Version 1.0DO NOT COPYCopyright SD Association, 2000, 20012.SDIO Signaling Definition2.1SDIO Card TypesThis specification defines two types of SDIO cards. The Full-Speed card supports SPI, 1-bit SD and the 4-bit SD transfer modes at the full clock range of 0-25MHz.

22、The Full-Speed SDIO devices have a data transfer rate of over 100 Mb/second (10 MB/Sec). A second version of the SDIO card is the Low-Speed SDIO card. This card requires only the SPI and 1-bit SD transfer modes. 4-bit support is optional. In addition, Low-Speed SDIO cards shall support a full clock

23、range of 0-400 KHz. The intended use of Low-Speed cards is to support low- speed IO devices with a minimum of hardware. The Low-Speed cards support such functions as modems, bar-code scanners, GPS receivers etc. If a card is a Combo card (memory plus SDIO) then Full-Speed and 4-bit operation is mand

24、atory for both the memory and SDIO portions of the card.2.2SDIO Card modesThere are 3 signaling modes defined for SD physical specification version 1.01 memory cards that also apply to SDIO Card:2.2.1SPI (Card mandatory support)The SPI bus topology is defined in section 3.1.2 and the protocol is def

25、ined in sections 3.2.2 and 7 of the SD Memory Card Specifications, PHYSICAL LAYER SPECIFICATION, Part 1,September 2000 Version1.01. In this mode pin 8, which is undefined for memory, is used as the interrupt pin. All other pins and signaling protocols are identical to the SD Memory specification.2.2

26、.21-bit SD data transfer mode (Card mandatory support)This mode is identical to the 1 data bit (narrow) mode defined for SD Memory in section 3.2.1 of the SD Memory Card specification. In this mode, data is transferred on the DAT0 pin only. In this mode pin 8, which is undefined for memory, is used

27、as the interrupt pin. All other pins and signaling protocols are identical to the SD Memory specification.2.2.34-bit SD data transfer mode (mandatory for High-Speed cards, optional for Low-Speed)This mode is identical to the 4 data bit mode (wide) defined for SD Memory in section 3.2.1 of the SD Mem

28、ory Card specification. In this mode, data is transferred on all 4 data pins (DAT3:0). In this mode the interrupt pin is not available for exclusive use as it is utilized as a data transfer line. Thus, if the interrupt function is required, a special timing is required to provide interrupts. See sec

29、tion 7.1.2 for details of this operation. The 4-bit SD mode provides the highest data transfer possible, up to 100 Mb/sec.2.3SDIO Host ModesIf a SDIO aware host supports the SD transfer mode, it is recommended that both the 1-bit and 4-bit modes be supported. While a SDIO host that supports only the

30、 4-bit transfer mode is possible, its performance with a Low-Speed SDIO card would be reduced. This is because the only means to transfer data to and from a Low-Speed card would be the single byte per command transfer (using the IO_RW_DIRECT command (CMD52) see 5.1).2SDIO Simple Specification Versio

31、n 1.0DO NOT COPYCopyright SD Association, 2000, 20012.4Signal PinsCLKCMDT3:0CLKCMDDAT3:0Figure 1 Signal connection to two 4-bit SDIO cardsTable 1 SDIO pin definitionsIt is recommended that multi-slot hosts intending to support SDIO (SDIO aware) provide a separate CLK to each slot, to allow the I/O d

32、evices to be placed in a low power state on a slot-by-slot basis. After reset, all data lines (DAT3:0) shall be in the hi-Z state on both the host and card(s) to avoid bus conflict. Access to the Bus Interface Control register within the CCCR determines DAT line mode.2.5Host Requirements for SDIOIn

33、order for a host to completely support all of the capabilities of the SDIO cards, some signal connections must be supported. In order to support interrupts, the host shall have Pin 8 connected from the card to the host in order to provide interrupt signaling. This is true even if the host will only

34、support the SPI or 1 bit SD mode. In addition, if the host supports more than 1 card in either SD mode, the CMD and all 4 data lines (DAT3:0) should not be bussed together, but rather routed separately to the host. This will allow the mixing of card types in the different sockets without interferenc

35、e. Both the SD Memory specification and the SDIO specification support the concept of “unifying” (connecting together) the CMD lines in a multi-slot system after initialization.3PinSD 4-bit modeSD 1-bit modeSPI mode1CD/DAT3Data line 3N/CNot UsedCSCard Select2CMDCommand lineCMDCommand lineDIData inpu

36、t3VSS1GroundVSS1GroundVSS1Ground4VDDSupply voltageVDDSupply voltageVDDSupply voltage5CLKClockCLKClockSCLKClock6VSS2GroundVSS2GroundVSS2Ground7DAT0Data line 0DATAData lineDOData output8DAT1Data line 1 or Interrupt (optional)IRQInterruptIRQInterrupt9DAT2Data line 2 or Read Wait (optional)RWRead Wait (

37、optional)NCNot UsedSD I/O CardSD I/O CardSD HostDSDIO Simple Specification Version 1.0DO NOT COPYCopyright SD Association, 2000, 20013.SDIO Card Initialization3.1Differences in I/O card initializationA requirement for the SDIO specification is that an SDIO card must not cause non-I/O aware hosts to

38、fail when inserted. In order to prevent operation of I/O Functions in non-I/O aware hosts, a change to the SD card identification mode flowchart is needed. A new command (IO_SEND_OP_COND, CMD5) is added to replace the ACMD41 for SDIO initialization by I/O aware hosts.After reset or power-up, all I/O

39、 functions on the card are disabled and the I/O portion of the card will not respond to any operation except CMD5 or CMD0 with CS=low. If there is SD memory installed on the card (also called a combo card), that memory will respond normally to all normal mandatory memory commands.An I/O only card wi

40、ll not respond to the ACMD41 and thus appear initially as an MMC card (See B.1 for information on the MMC specification). The I/O only card will also not respond to the CMD1 used to initialize the MMC cards and appear as a non-responsive card. The host will then give up and disable this device Thus,

41、 the non-aware host will receive no response from an I/O only card and force it to the inactive state.An SDIO aware host will send CMD5 prior to the CMD55/ACMD41 pair, and thus would receive a valid OCR in the R4 response to CMD5 and continue to initialize the card. Figure 2 shows the operation of a

42、n SDIO aware host operating in the SD modes and Figure 3 shows the same operation for a host that operates in the SPI mode.If the I/O portion of a card has received no CMD5, the I/O section remains inactive and will not respond to any command except CMD5. A combo card stays in the memory-only mode.

43、If no memory is installed on the card (i.e. an I/O only card in a non-SDIO aware host) the card would not respond to any memory command. This satisfies the condition where a user uses some I/O function on the card such as Ethernet to load a music file to the memory function of that card. The card is

44、 then removed and inserted into a non-SDIO aware host. That device would not enable the I/O function (no CMD5) so would appear to the player as a memory-only card. If the host were I/O aware, it would send the CMD5 to the card and the card would respond with R4. The host reads that R4 value and know

45、s the number of available I/O functions and about the existence of any SD memory.The function of CMD5 for SDIO cards is similar to the operation of ACMD41 for SD memory cards. It is used to inquire about the voltage range needed by the I/O card. The normal response to CMD5 is R4 in either SD or SPI

46、format. The I/O aware host will send CMD5. If the card responds with response R4, the host determines the cards configuration based on the data contained within the R4.After the host has initialized the I/O portion of the card, it then reads the Common Information Area (CIA) of the card (see 6.7). T

47、his is done by issuing a read command, starting at byte 00 of I/O function 0. The CIA contains the Card Common Control Registers (CCCR) and the Function Basic Registers (FBR). Also included in the CIA are pointers to the cards common Card Information Structure (CIS) and each individual functions CIS

48、. The CIS includes information on power, function, manufacturer and other things the host needs to determine if the I/O function(s) is appropriate to power-up. If the host determines that the card should be activated, a register in the CCCR area enables the card and each individual function. At this

49、 time, all functions of the I/O card are fully available. In addition, the host can control the power consumption and enable/disable interrupts on a function-by-function basis. This access to I/O will not interfere with memory access to the card if present.4SDIO Simple Specification Version 1.0DO NO

50、T COPYPo w e r O NCopyright SD Association, 2000, 2001IO= 0 , ME M= 0 , P I= 0 NoIn it IO ?Ye s IO = 0 R e in it IOCM D5arg = 0if N R o r (F = 0 & M P = 1 )if F = 0 & M P =0if F 0if O C R in va lid & M P = 0if O C R in va lid & M P = 1Te s t IO OC RO CR va lidIO R D Y = 0if tim e ou tCM D5arg = W VI

51、n a c tive S ta teif N Rif IO R D Y = 1 (IO = 1 )IO RDY t im e o u t in d ica te s IO fa ilu reif P I=1 o r M P =0Test MPif P I= 0 an d M P = 1In itMe m o ry?N oYe sM E M = 0 R e in it Me m o ryif N RACM D 4 1a rg= 00Ge t m e m OCRVa ria b le sN u m b e r of IO function s N o R e s p onseI/O P o w e

52、 r-u p s ta tu s is re a d y (Cif m e m O C R in va lidF:NR:IO R D Y :Te s t m em OC Rbit in the re s p onse C M D 5 )me m O C R va lidM RDY :M e m o ry pow e r-up statu s isre a d y (B it31 of O C R )Fla g sI/O F u n c tio n s in itia lize d fla g M e m o ry in itia liz e d fla gM e m o ry exis ts

53、flag (in th e re s p onse of C M D 5 )P o w e r O n In itia liz a tio nIlle gal c o m m a nd R e s p o n s eIO : ME M : MP :ME MR D Y = 0if N RACM D 41arg = W Vif ME MR D Y tim e o u tIn a c tive S ta tePI:IR :if ME MR D Y (M E M = 1 )IO o r M E M = 1Te s t flag sIO = 0 ,M E M = 0T est fla g sMM CCa

54、 rdMe m on lyI/ O on lyCo m boIn a c tive S ta teMP = 0 , IO = 0S ta rt in itia liza tio n w ith CM D0 , CM D 1IO = 0 , M E M = 1IO = 1 , ME M= 1IO = 1 , M E M = 0Figure 2 Card initialization flow in SD mode (SDIO aware host)5CM D1 5CM D3P I= 1 CM D2Se t newVo lta ge (if ne ed ed )CM D0Se t newVo lt

55、a geCM D5 2I/O R e s e tSDIO Simple Specification Version 1.0DO NOT COPYIO=0, MEM=0, PI=0Copyright SD Association, 2000, 2001 Power ON NoInit IO?IO=0YesReinit IO if IR or (F=0 & MP=1)CMD5if (F=0 & MP=0)arg=0if F0Test IO OCRif OCR invalid & MP=0 if OCR invalid & MP=1No voltage compare performed by card for CMD5OCR ValidIORDY=0if (IR or timeout) & MP=0if (IR or timeout) & MP=1CMD5arg=WVIORDY timeout indicates IO failureif IORDY (IO=1)Test MPif PI=1 or MP