dc synopsys workshoppptdc1_200703_sg_08_timing_analysis

1、AgendaDAY567898- 1Synopsys 10-I-011-SSG-013 2007 Synopsys, Inc. All Rights ReservedMore Constraint ConsiderationsTiming AnalysisCompile CommandsEnvironmental AttributesPartitioning for Synthesis2Unit ObjectivesAfter completing this unit you should be able to:n Generate timing reports, with additiona

2、l command options as needed, to diagnose timing constraint violations8- 2RTL Synthesis Flow8- 3Write out design dataSynthesize the design Optimze AnalyzeSelect appropriate compile flowApply design constraintsCreate constraints fileCreate start-up fileLoad designs and librariesWrite RTL code and simu

3、lateCommands Covered in this Unit8- 4report_timing -delay max | min -to pin_port_clock_list -from pin_port_clock_list -through pin_port_list -group -input_pins -max_paths path_count -nworst paths_per_endpoint_count -nets -capacitance -significant_digits numberTiming ReportsSee Appendix for more deta

4、ilsThe report_timing command:n Breaks the design down into individual timing pathsn Analyzes each timing path at least twice for single-cycle max-delay timing Rising endpoint and falling endpointn Generates a default, four-section report which includes: One path, the worst violator1, per path group2

5、 Maximum delay or setup timing onlyu No hold timingu No DRCu No area8- 5Timing Report: Path Information Section8- 6* Report : timing-path full-delay max-max_paths 1 Design : TTVersion: 2007.03Date: Tue Mar 20 16:48:52 2007*Operating Conditions: slow_125_1.62Library: ssc_core_slow Wire Load Model Mod

6、e: enclosedStartpoint: data1 (input port clocked by clk)Endpoint: u4 (rising edge-triggered flip-flop clocked by clk) Path Group: clkPath Type: maxDes/Clust/PortWire Load ModelLibraryTT5KGATESssc_core_slowTiming Report: Path Delay SectionIndividual Contribution to Path DelayRunning Total of the Path

7、 DelaySignal TransitionArrival TimeNet & Cell DelaysTime-of-flight0.110.01DDdata1Yu4u2u1u23u128- 7PointIncrPathclock clk (rise edge)0.000.00clock network delay (ideal)0.500.50input external delay1.001.50 fdata1 (in)0.041.54 fu2/Y (inv1a1)0.121.66 ru12/Y (or2a1)0.261.92 ru23/Y (mx2d2)0.232.15 fu4/D (

8、fdef1a1)0.002.15 f data arrival time2.15Timing Report: Path Required SectionClock EdgeFrom the LibraryData must be valid by this time8- 8PointIncrPathclock clk (rise edge)2.002.00clock network delay (ideal)0.502.50clock uncertainty-0.272.23U4/CLK (fdef1a1)0.002.23library setup time-0.062.17data requ

9、ired time2.17Timing Report: Summary SectionTiming margin or slack: (positive number = met negative number = violation)Either (MET) or (VIOLATED)8- 9data required time2.17data arrival time-2.15slack (MET)0.02Timing Report: Optionsreport_timing-delay max/min -to pin_port_clock_list-from pin_port_clock

10、_list -through pin_port_list -group-input_pins -max_paths path_count -nworst paths_per_endpoint_count-nets -capacitance -significant_digits number .8- 10Can you guess which option reports cell and net delays separately?The default behavior of report_timing is to report the path with the worst slack

11、within each path group.Example -nworst vs. -max_pathsSlack = -0.3CLK1Slack = -0.25Slack = -0.15Slack = -0.05CLK1What is the WNS in this example?Which paths are reported with report_timing? Which paths will be reported with report_timing2?-max_pathsWhat changes with report_timing -nworst 2-max_paths

12、2?8- 11Timing Analysis ExercisePointIncrPathclock clock inputclk (rise edge) network delay (ideal) external delay0.000.808.400.040.000.000.620.750.330.790.000.001.340.480.680.000.000.000.111.281.440.170.030.000.809.209.249.249.249.8610.6110.9411.7311.7311.7313.0713.5514.2314.2314.2314.2314.3415.6217

13、.0617.2317.2617.26f f f f r f f r r r f r r r r r f r f r raddr31 (in)u_proc/address31 (proc)u_proc/u_dcl/int_add7(dcl)u_proc/u_dcl/U159/Q u_proc/u_dcl/U160/Q u_proc/u_dcl/U186/Q u_proc/u_dcl/U135/Q(NAND3H) (NOR3F) (AND3F) (NOR3B)u_proc/u_dcl/ctl_rs_N (dcl) u_proc/u_ctl/ctl_rs_N (ctl)u_proc/u_ctl/U1

14、26/Q u_proc/u_ctl/U120/Q u_proc/u_ctl/U122/Q(NOR3B) (NAND2B) (OR2B)u_proc/u_ctl/read_int_N u_proc/int_cs (proc)(ctl)u_int/readN u_int/U17/Q u_int/U16/Q u_int/U60/Q u_int/U68/Q(int)(INVB) (AOI21F) (AOI22B) (INVB)u_int/int_flop_0/D data arrival time(DFF)clock clock clockclk (rise edge) network delay (

15、ideal) uncertainty12.500.80-0.450.00-0.1212.5013.3012.8512.8512.7312.73u_int/int_flop_0/CLK library setup time data required time(DFF)r8- 12slack (VIOLATED)-4.53Identify two items which can potentially be addressed toimprove the slack .Analysis RecommendationsAfter each compile or optimization stepn

16、 Use report_constraintall to determine all theconstraint violations in your designn Use report_timing, with appropriate options, to analyze violating timing paths in more detail8- 13Summary: Commands Covered8- 14report_timing -delay max | min -to pin_port_clock_list -from pin_port_clock_list -throug

17、h pin_port_list -group -input_pins -max_paths path_count -nworst paths_per_endpoint_count -nets -capacitance -significant_digits numberSummary: Unit ObjectivesYou should now be able to:n Generate timing reports, with additional command options as needed, to diagnose timing constraint violations8- 15

18、AppendixStatic Timing Analysis FundamentalsStatic Timing Analysis: What Tool Do I Use?n Design Compiler has a built-in static timing analyzern STA is used During compile to guide optimization decisions After compile to generate timing and timing-related reportsVHDLVerilog8- 17Design CompilerStatic T

19、iming AnalyzerVHDL Compiler (Presto)HDL Compiler (Presto)Static Timing Analysisn Static Timing Analysis can determine if a circuit meets timing constraints without dynamic simulationn This involves three main steps: The design is broken down into timing paths The delay of each path is calculated All

20、 path delays are checked against timing constraints to determine if the constraints have been met8- 18Path 1Path2ADQZCLKPath 3Grouping of Timing Paths into Path GroupsMY_DESIGNZpath1path2path3ADQDQDQFF2FF3FF4QBQBQBCLK1 CLK2CLK3 path4 Timing PathsPath GroupsPaths are grouped by the clocks controlling

21、 their endpoints8- 19CLK1path1CLK2CLK3path2path3path4Example: Timing Paths and Group PathsHow many timing paths are there?How many path groups are there?Path Group CLK_1CLK_3Path Group CLK_311 timing paths3 path groupsPath Group CLK_2CLK_1CLK_28- 20Schematic Converted to a Timing GraphTo calculate t

22、he total delay, Design Compiler breaks each path into timing cell and net delay arcs: Cell delays are typically calculated using non-linear delay models defined in the library Net delays are calculated based on WLMs or DC-Topographical estimates, and interconnect delay models defined in the library8- 21Edge Sensitivity in Path DelaysThere is an “edge sensitivity”