SystemVerilog硬件设计及建模—第10章概要.ppt

1、SystemVerilog在Verilog语言基础上扩展了“接口”（interface）结构，接口给模型提供了一种新的方式，通过使用接口可以简化大型复杂设计的建模和验证。,接口声明 接口与模块端口之间的连接 接口与模块的区别 接口的端口及其方向 接口中的任务与函数 接口方法的使用 接口中的过程块 参数化的接口,第10章 接口,10.1 接口的概念,接口反映的是模块与模块之间的互连，对Verilog来说，主要通过模块的端口表现。,10.1 接口的概念,module top (input wire clock, resetn, teset_mode); wire 15 : 0 data, addr

2、ess, program_addr, jump_addr; wire 7 : 0 instr, next_instr; wire 3 : 0 slave_instr; wire slave_req, slave_rdy; wire bus_req, bus_grant; wire mem_read, mem_write; write data_rdy; processor proc1 ( /main_bus ports .data(data), .address(address), .slave_instr(slave_instr), .slave_req(slave_req), .bus_g

3、rant(bus_grant), .mem_read(mem_read), .mem_write(mem_write), .bus_req(bus_req), .slave_rdy(slave_rdy), /other ports .jump_addr(jump_addr), .instr(instr), .clock(clock), .resetn(resetn), .test_mode(test_mode);,10.1 接口的概念,slave slave1 ( /main_bus ports .data(data), .address(address), .bus_req(bus_req)

4、, .slave_ready(slave_ready), .mem_read(mem_read), .mem_write(mem_write), .slave_instr(slave_instr), .slave_req(slave_req), .bus_grant(bus_grant), .data_rdy(data_rdy), / other ports .clock(clock), .resetn(resetn); dual_port_ram ram ( / main_bus ports .data(data), .data_rdy(data_rdy), .address(address

5、), .mem_read(mem_read), .mem_write(mem_write), / other ports .program_addr(program_addr), .data_b(next_instr);,10.1 接口的概念,test_generator test_gen( / main_bus ports .data(data), .address(address), .mem_read(mem_read), .mem_write(mem_write), / other ports .clock(clock), .resetn(resetn), .test_mode(tes

6、t_mode); instruction_reg ir ( .program_addr(program_addr), .instr(instr), .jump_addr(jump_addr), .next_instr(next_instr), .clock(clock), .resetn(resetn); endmodule,10.1 接口的概念,module processor ( / main_bus ports inout wire 15:0 data, output reg 15:0 address, output reg 3:0 slave_instr, output reg sla

7、ve_req, output reg bus_grant, output wire mem_read, output wire mem_write, input wire bus_req, input wire slave_rdy, / other ports output reg 15:0 jump_addr, input wire 7:0 instr, input wire clock, input wire resetn, input wire test_mode); . / module functionality code endmodule,module slave ( / mai

8、n_bus ports inout wire 15:0 data, inout wire 15:0 address, output reg bus_req, output reg slave_rdy, output wire mem_read, output wire mem_write, input wire 3:0 slave_instr, input wire slave_req, input wire bus_grant, input wire data_rdy, / other ports input wire clock, input wire resetn); . / modul

9、e functionality code endmodule,10.1 接口的概念,module dual_port_ram ( / main_bus ports inout wire 15:0 data, output wire data_rdy, input wire 15:0 address, input tri0 mem_read, input tri0 mem_write, / other ports input wire 15:0 program_addr, output reg 7:0 data_b); . / module functionality code endmodul

10、e,module test_generator ( / main_bus ports output wire 15:0 data, output reg 15:0 address, output reg mem_read, output reg mem_write, / other ports input wire clock, input wire resetn, input wire test_mode); . / module functionality code endmodule,10.1 接口的概念,module instruction_reg ( output reg 15:0

11、program_addr, output reg 7:0 instr, input wire 15:0 jump_addr, input wire 7:0 next_instr, input wire clock, input wire resetn); . / module functionality code endmodule,10.1.1 Verilog模块端口的缺点,Verilog模块的端口提供了一种描述设计中模块之间连接关系的方式，这种方式直观明了，但在大型复杂设计中，有很多缺点： 在多个模块中必须重复声明端口 在不同模块中有声明不匹配的风险 设计规范中的一个改动需要修改多个模块

12、在多个模块中通信协议也必须重复 例如有三个模块对一个共享存储器进行读写操作，那么在这三个模块中，读写操作的控制逻辑必须重复描述 限制了抽象的自顶向下的设计 用模块端口连接时，设计的具体互连必须在设计周期的早期确定，而不能在一个不需要考虑设计细节的抽象层面上描述。,10.1.2 SystemVerilog接口优势,SystemVerilog增加了新的端口类型接口，接口允许许多信号合成一组由一个端口表示，只需在一个地方对组成接口的信号进行声明，使用这些信号的模块只需一个接口类型的端口。 interface main_bus; wire 15:0 data; wire 15:0 address; l

13、ogic 7:0 slave_instr; logic slave_req; logic bus_grant; logic bus_req; logic slave_rdy; logic data_rdy; logic mem_read; logic mem_write; endinterface,10.1.2 SystemVerilog接口优势,module top (input logic clock, resetn, test_mode); logic 15:0 program_addr, jump_addr; logic 7:0 instr, next_instr; main_bus

14、bus ( ); / instance of an interface / (instance name is bus) processor proc1 ( / main_bus ports .bus(bus), / interface connection / other ports .jump_addr (jump_addr), .instr (instr), .clock(clock), .resetn(resetn), .test_mode(test_mode);,10.1.2 SystemVerilog接口优势,slave slave1 ( / main_bus ports .bus

15、(bus), / interface connection / other ports .clock(clock), .resetn(resetn); dual_port_ram ram ( / main_bus ports .bus(bus), / interface connection / other ports .program_addr (program_addr), .data_b(next_instr);,10.1.2 SystemVerilog接口优势,test_generator test_gen( / main_bus ports .bus(bus), / interfac

16、e connection / other ports .clock(clock), .resetn(resetn), .test_mode(test_mode); instruction_reg ir ( .program_addr (program_addr), .instr(instr), .jump_addr(jump_addr), .next_instr(next_instr), .clock(clock), .resetn(resetn); endmodule,10.1.2 SystemVerilog接口优势,module processor ( / main_bus interfa

17、ce port main_bus bus, / interface port / other ports output logic 15:0 jump_addr, input logic 7:0 instr, input logic clock, input logic resetn, input logic test_mode); . / module functionality code endmodule module slave ( / main_bus interface port main_bus bus, / interface port / other ports input

18、logic clock, input logic resetn); . / module functionality code endmodule,module dual_port_ram ( / main_bus interface port main_bus bus, / interface port / other ports input logic 15:0 program_addr, output logic 7:0 data_b); . / module functionality code endmodule module test_generator ( / main_bus interface port main_bus bus, / interface port / other ports input logic c