Chap10逻辑综合与时序仿真.ppt

1、Unit 4 VLSI设计方法,Chap10 逻辑综合与时序仿真,Unit 1 绪论Unit 2 CMOS电路设计基础Unit 3 CMOS电路的逻辑设计Unit 4 VLSI设计方法 Chap8 设计模式和设计流程 Chap9 RTL设计与仿真 Chap10 逻辑综合与时序仿真 Chap11 可测试性设计与ATPG Chap12 版图设计与验证,Specification Executable model RTL code Gate-level netlist Cell/interconnect level position Mask-level geometry,System (Behav

2、ioral) level RTL Gate (Logic) level Layout (Physical) Level,设计阶段 （设计抽象层）,设计结果,Logic Design & Simulation : from RTL, then in Gate-Level,Logic Synthesis 得到用已有的基本逻辑单元（库单元）互联并满足一定逻辑功能的逻辑构成 Gate-Level Simulation（门级功能仿真与动态时序分析） 一般不做这一步 Formal Verification（形式验证） STA（Static Timing Analysis，静态时序分析）,HDL Codin

3、g for SynthesisBased on Synopsys Design Compiler,The Importance of Quality of Source Code,Codes that are functionally equivalent, but coded differently will give different synthesis results. You cannot rely solely on Design Compiler to “fix” a poorly coded design! Try to understand the “hardware” yo

4、u are describing, to give DC the best possible starting point.,Think Hardware!,Write HDL hardware descriptions Think of the topology implied by the code Do not write HDL simulation models No explicit delays No file I/O,Think Synchronous!,Synchronous designs run smoothly through synthesis, simulation

5、, test, and layout Asynchronous designs may require hand instantiation and extensive simulation to verify Isolate asynchronous logic into separately compiled blocks,Think RTL!,Writing in an RTL coding style means describing: the circuit topology the register placement the functionality between regis

6、ters DC optimizes logic between registers: It does not optimize the register placement,Synthesis of if Statements(1),The if-else construct implies multiplexing hardware,Actual circuit implementation depends on target library and Constraints,Synthesis of if Statements(2),To infer latches, use an if s

7、tatement without an else clause,Synthesis of case Statements,imply parallel mux function,Synthesis of Flip-Flops,Synthesis of Flip-Flops,SynthesisBased on Synopsys Design Compiler,0. Introduction to Synthesis 1. Pre-Synthesis Processes 2. Constraining the Design 3. Synthesizing the Design,What Is Sy

8、nthesis?,Synthesis is the transformation of an idea into a manufacturable device to carry out an intended function.,在包含众多结构、功能、性能均已知的逻辑单元电路的目标工艺库的支持下 得到目标工艺库中单元电路的连接关系（逻辑网络）的最佳实现方案 满足设计电路的功能要求以及速度、面积等限制条件,Synthesis Internal Flow,Synthesis Is Constraint-Driven,Synthesis Is Path-Based,0. Introduction

9、to Synthesis Pre-Synthesis Processes Technology Library for synthesis Design Hierarchy and Partition 2. Constraining the Design 3. Synthesizing the Design,Technology Library (1),工艺库由Foundary提供，一般是.db的格式，这种格式是DC认识的一种内部文件格式，不能由文本方式打开 .db格式可以由文本格式.lib转化过来,Technology Library (2),During mapping, DC will:

10、 choose functionally-correct gates from this library calculate the timing of the circuit using vendor-supplied timing data for these gates target_library is a reserved variable in DC，you should set it to point to the Technology library file(s) provided by your silicon vendor,Design Hierarchy: RISC_C

11、ORE example,Design Hierarchy (Partitioning) within HDL Description,编写HDL代码之前（系统设计阶段）都需要系统划分，根据功能或者其他的原则将一个系统层次化地分成若干个模块，这些模块内部再进一步细分成模块/子模块 Entity (VHDL) and module (Verilog) statements define hierarchical blocks. Inference of Arithmetic Circuits (+, -, *, .) can create a new level of hierarchy. Pro

12、cess (VHDL) and always (Verilog) statements do not create hierarchy,Repartitioning to Design Hierarchy for Synthesis,在DC做综合的过程中，默认的情况下各个模块的层次关系是保留着的。保留着的层次关系会对DC综合造成一定的影响，比如在优化的过程中，各个模块的管脚必须保留，这势必影响到模块边界的优化效果,Why Partitioning/ Repartitioning,Partitioning or Repartitioning is driven by many (often co

13、mpeting) needs: Separate distinct functions Achieve workable size and complexity Manage project in team environment Design Reuse Meet physical constraints And many, many others,Poor Partitioning: so Should Eliminate Unnecessary Hierarchy,Good Partitioning(1): No Hierarchy in Combinational Paths,Good

14、 Partitioning(2): No Hierarchy in Combinational Paths,Good Partitioning(3): Partition at Register Boundaries,Example(1): Avoid Glue Logic,Example(2): Remove Glue Logic Between Blocks,Balance Block Size in Partitioning(1),Balance Block Size in Partitioning(2),Top-Level Design Partitioning,Repartition

15、ing within Design Compiler,The group and ungroup commands modify the partitions in a design. Group creates a new hierarchical block. Ungroup removes either one or all levels of hierarchy.,Group,Ungroup,0. Introduction to Synthesis 1. Pre-Synthesis Processes 2. Constraining the Design Area Constraint

16、s Timing Constraints and Time Budgeting Environmental Attributes Clock Constraints 3. Synthesizing the Design,Specifying Area Constraints,施加了一个最大面积100单位的约束 Units are those of target library, defined by the vendor: 2-input-NAND-gate transistors square mils,Specify Timing Constraints (1),Synchronous D

17、esigns: Data arrives from a clocked device Data goes to a clocked device Objective: Define the timing constraints for all paths within a design: 1. The internal (register to register) paths 2. All input paths 3. All output paths,Specify Timing Constraints (2),1. Creating a clock constrains timing pa

18、ths between registers create_clock -period 10 get_ports Clk,Specify Timing Constraints (3),2. Constraining the Input Paths set_input_delay max (input delay) clock Clk get_ports Clk,Specify Timing Constraints (4),3. Constraining Output Paths set_output_delay max (output delay) clock Clk get_ports Clk

19、,Time Budgeting (1),What if you do not know the delays on your inputs or the setup requirements of your outputs? Create a Time Budget !,Time Budgeting (2),Time Budgeting,Time Budgeting: Example Time Budgeting for MY_BLOCK Time Budgeting for X_BLOCK and Y_BLOCK,Time Budgeting (3),Constraining for Tim

20、ing: What Is Missing?,输入输出的电平转换时间(transition time)由输入外围电路的驱动能力和输出外围电路的负载大小决定 电路内部的互连线时延的估计 当外界温度或者电路供电电压发生变化时，时延会相应的改变,Environmental Attributes (1),set_driving_cell: Input Drive Strength,Environmental Attributes (2),set_load: Output Capacitive Load,Environmental Attributes (3),set_wire_load_model: N

21、et Delays,A Wire Load Model (WLM) is an estimate of a nets RC parasitics based on the nets fanout: Model is created by your vendor Estimates are based on statistics from other designs the vendor has fabricated using this process Specifying WLM in Design Compiler,Environmental Attributes (4),Operatin

22、g Conditions Why? Library cells are usually characterized using “nominal” voltage and temperature. If not What? Vendors allow for synthesis of circuits which will not operate under “nominal” conditions by embedding other operating conditions in the technology libraries vendor-supplied operating cond

23、itions (vendors might deliver multiple technology libraries ),Operating Conditions To set operating conditions, enter set_operating_conditions command During synthesis, “nominal” cell and wire delays will be scaled based on the operating conditions,Clock Constraints (1),Recall Timing Constraints,Clo

24、ck Constraints (2),对时钟网络进行综合时，需要在时钟的各条路径上要插入大小不一的buffer，目的是为了保证时钟到达每个触发器的时延尽量相等 在定义时钟之后，都要给该时钟设置dont_touch，告诉DC不要对时钟网络进行综合（插入Buffer）。这是因为综合时钟网络需要考虑单元的实际物理位置，这是前端的逻辑综合（DC）不能完成的工作,Clock Constraints (3),Modeling Clock Skew 虽然DC无法最终综合时钟树，但是可以加入一些约束让此时的时钟更加接近实际的工作情况 实际的时钟达到各个触发器的时间不是一样的，它们之间的偏差称为时钟偏差(Clo

25、ck Skew)。为了反映这个偏差，我们在综合时可以用一个命令来模拟它,Clock Constraints (4),Modeling Source Latency Clock到达模块的端口后，要到达内部的触发器，也要经过一定的延时，这个延时称为Network Latency,0. Introduction to Synthesis 1. Pre-Synthesis Processes 2. Constraining the Design 3. Synthesizing the Design Multiple Instances How to Compile a Hierarchical Des

26、ign Timing Analysis and Report,Multiple Instances (1),Designs Instantiated More Than Once uniquify compile + dont_touch,Multiple Instances (2),uniquify vs. compile + dont_touch compile+dont_touch 由于只需对多次例化的模块编译一次，可以减少整个设计的编译时间，减少内存的使用量。在多次例化的模块很复杂并且工作站硬件条件有限的情况下，其优越性比较明显。如果这个Ades是一个第三方提供的IP硬核(hard-c

27、ore)，那么也只能使用这种方法 在编译顶层模块时，由于Ades设置了dont_touch，这就妨碍了DC针对Ades的各个实例周围环境的不同的进一步优化，从而使得结果不能真实反映各个实例周围的环境变化 Uniquify 由于把各个多例化模块作为独立的模块来看，因此DC可以分别针对它们作出更好的优化，从而得到的结果比较理想 编译的时间稍微较长，但是对于一些不大的模块来说，这些是可以忽略的。 一般推荐使用uniquify解决多例化模块的综合问题。,Compiling a Hierarchical Design (1),对一个大型设计来讲，有两种层次化编译技术 自上而下(Top-down) 将整个

28、设计一次性读入，施加顶层约束后直接进行编译 无需考虑各个模块/子模块之间的依赖关系，也就不需要制模块/子模块之间的时序预算和负载预算，都由DC自动考虑 编写脚本变得简单，维护起来也比较方便 自下而上(Bottom-up) 先单独编译各个模块/子模块：在编译要考虑与其它模块之间的关系，给它们加入时序预算和负载预算，看是否满足约束 再读入顶层文件，施加顶层约束，将各个模块/子模块整合起来：顶层编译完成后还必须看顶层约束是否满足,Compiling a Hierarchical Design (2),Pros & Cons of Bottom-Up Compile 优点 利用”分而治之”的策略，对于

29、大型的不可能一次编译的设计十分有用 摆脱了Top-down方法的对工作站硬件条件的限制，使得大型设计也能在一般的机器上编译完成 缺点 实现步骤比较多，尤其对各个模块之间的时序和负载预算要求很高 Summary,Timing Analysis and Report (1),What Tool to Use? Design Compiler has a built-in static timing analyzer called DesignTime,Timing Analysis and Report (2),DesignTime Timing Reports,Logic Design & Si

30、mulation : from RTL, then in Gate-Level,Logic Synthesis 得到用已有的基本逻辑单元（库单元）互联并满足一定逻辑功能的逻辑构成 Gate-Level Simulation（门级功能仿真与动态时序分析） 一般不做这一步 Formal Verification（形式验证） STA（Static Timing Analysis，静态时序分析）,STA Based on Synopsys PrimeTime,What is Static Timing Analysis?,Static Timing Analysis（STA）determines if a circuit meets timing constraints without dynamic simulation Three main steps: Design is broken down into sets of timing paths The delay of each path is calculated All path delays are checked to see if timing constraints have been met,STA Step 1: Timing Paths,Step1实际是将逻辑电路网表转换成拓扑图，图