组合函数及相应电路

Chapter3CombinationalLogicDesignIILogicandComputerDesignFundamentalsChapter42OverviewFunctionsandfunctionalblocksRudimentarylogicfunctionsDecodingEncodingSelectingChapter43FunctionsandFunctionalBlocksThefunctionsconsideredarethosefoundtobeveryusefulindesignCorrespondingtoeachofthefunctionsisacombinationalcircuitimplementationcalledafunctionalblock.Inthepast,manyfunctionalblockswereimplementedasSSI,MSI,andLSIcircuits.Today,theyareoftensimplypartswithinaVLSIcircuits.Chapter44RudimentaryLogicFunctionsFourelementarycombinationallogicfunctionsValue-Fixing:F=0orF=1,noBooleanoperatorTransferring:F=X,noBooleanoperatorInverting:F=X,involvesonelogicgateEnabling:F=X·ENorF=X+EN,involvesoneortwologicgatesThefirstthreearefunctionsofasinglevariableX01F=

0F=

1(a)F=

0F=

1VCC

orVDD(b)XF=

X(c)XF=

X(d)Table4-1FunctionsofonevariableXF=0F=XF

=F=10100011011XChapter45Multiple-bitRudimentaryFunctionsMulti-bitExamples:Awidelineisusedtorepresent

abuswhichisavectorsignalIn(b)oftheexample,F=(F3,F2,F1,F0)isabus.Thebuscanbesplitintoindividualbitsasshownin(b)Setsofbitscanbesplitfromthebusasshownin(c)

forbits2and1ofF.Thesetsofbitsneednotbecontinuousasshownin(d)forbits3,1,and0ofF.F(d)0F31F2F1AF0(a)01A1234F0(b)42:1F(2:1)2F(c)43,1:0F(3),F(1:0)3AAChapter46EnablingFunctionEnablingpermitsaninputsignaltopassthroughtoanoutputDisablingblocksaninputsignalfrompassingthroughtoanoutput,replacingitwithafixedvalueThevalueontheoutputwhenitisdisablecanbeHi-Z(asforthree-statebuffersandtransmissiongates),0,or1Whendisabled,0outputWhendisabled,1outputSeeEnablingAppintextXFEN(a)ENXF(b)Chapter47DecoderDecoding-theconversionofann-bitinputcodetoanm-bitoutputcodewithn£m£2nsuchthateachvalidcodewordproducesauniqueoutputcodeCircuitsthatperformdecodingarecalleddecodersVariableDecoderDisplayDecoderTypesChapter48DecoderControllerWhat’sthebitlengthofdata?？01234567Chapter49DecoderABCY0Y1Y2Y3Y4Y5Y6Y70001000000000101000000010001000000110001000010000001000101000001001100000001011100000001Chapter410DecoderDecoding-theconversionofann-bitinputcodetoanm-bitoutputcodewithn£m£2nsuchthateachvalidcodewordproducesauniqueoutputcodeDecoders:

decoderwith2inputand4output,74LS139(2-to-4-LineDecoder)decoderwith3inputand8output,74LS138(3-to-8-LineDecoder)decoderwith4inputand16output,MC14514(4-to-16-LineDecoder)Chapter4111-to-2-LineDecoder2-to-4-LineDecoder

Notethatthe2-4-line

madeupof21-to-2-

linedecodersand4ANDgates.DecoderExamplesA10011A00101D01000D10100D20010D30001(a)D0=

A1

A0D1=

A1

A0D2=

A1

A0D3=

A1

A0(b)A1A0AD0D1010101(a)(b)D1=

AAD0=

AChapter412DecoderExpansionDeciderwithninputcanhave2noutput.Whennislarge,thecircuitisverycomplex.Generalprocedure:Letk=n.Ifkiseven,dividekby2obtaink/2.Use2kANDgatesdrivenbytwodecodersofoutputsize2k/2.Ifkisodd,obtain(k+1)/2and(k-1)/2.Use2kANDgatesdrivenbyadecoderofoutputsize2(k+1)/2andadecoderofoutputsize2(k-1)/2.Foreachdecoderresultingfromstep2,repeatstep2withkequaltothevaluesobtainedinstep2untilk=1.Fork=1,usea1-to-2decoder.Stillvalidwhenoutput≠2nChapter413Example:3-to-8-LineDecoder3-to-8-LineDecoderConstructdirectly,drive83-inputANDsHierarchically,dividetheinputsignalsequally2-to-4-Linedecoder1-to-2-Linedecoder2-to-4-LineDecoderdrive42-inputANDsdividetheinputsignalsequally1-to-2-LinedecoderChapter414Circuitof3-to-8-LineDecoderResultChapter415Example:7-to-128-LineDecoder7-to-128-LineDecoder1287-inputANDsareneededifconstructeddirectlyHierarchically,level1:4-to-16-LineDecoder3-to-8-LineDecoder4-to-16-Linedecoder162-inputANDsLevel2:22-to-4-LineDecoderConstructedbytheknown3-to-8-LineDecodersand2-to-4-LineDecodersChapter416Ingeneral,attachm-enablingcircuitstotheoutputsSeetruthtablebelowforfunctionNoteuseofX’stodenoteboth0and1CombinationcontainingtwoX’srepresentfourbinarycombinationsAlternatively,canbeviewedasdistributingvalueofsignalENto1of4outputsInthiscase,calleda

demultiplexer

DecoderwithEnableENA1A0D0D1D2D3(b)ENA1A0D0D1D2D301111X0011X010101000001000001000001(a)Chapter417CodeTranslationDecoderTranslatedatafromonecodesystemtoanother.CommonDecoders:Binary-coded→

DecimalBinarycodetodecimal(8421code)ordecimaldecoder(BCD

decoder)Excess3Code

todecimalcodedecoderChapter418BCD-to-DecimalDecodersBCD-to-DecimalDecodersisadecoderwhoseinputis4-bitBCDcodeandoutputisdecimalcode.4-bitbinarycodeshave16combinations,andBCDcodetakesthefirst10combinationswhiletheother6areunused.Table:Decimalto8421CodeDecimalCode8-4-2-1Code01234567890000000100100011010001010111010000111010Chapter419Twostrategiestodealwiththe6unusedcombinationsmakestwoBCD-to-DecimalDecodersIncompletelyDecodedBCD-to-DecimalDecoder:Onlyuse10combinationsCompletelyDecodedBCD-to-DecimalDecoder:All16combinationsareusedChapter420IncompletelyDecodedBCD-to-DecimalDecoderTruthtable

CircuitABCDY0Y1Y2Y3Y4Y5Y6Y7Y8Y9010000000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000135724689Chapter421CompletelyDecodedBCD-to-DecimalDecoderABCDY0Y1Y2Y3Y4Y5Y6Y7Y8Y901000000000000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000000000000000000000001111111111111111100111111111111111111111111111111111111111111111111111111111111不用0135724689NoEnablingsinbothtypesofBCD-to-DecimaldecodersChapter422DisplayDecoderSomecalculatorsanddevicesrequiretoshowthenumbers.DisplaydecodersdealwithbinaryorBCDinputsandoutputthedisplaysignaltodrivethedisplaydevicesThewidelyused7-segmentdisplayDigitalTubetypes:CommonCathodeandCommonAnodeCommonElectrodeCommonElectrodeabcdefghChapter423CommonelectrodeCommonelectrodeabcdefghCommonCathodeCommonAnode“1”aRGND“0”aRVCC=5VLED

DisplayChapter424TheCommonAnodeDisplay(CAD)AlltheanodeconnectionsoftheLED'sarejoinedtogethertologic"1"andtheindividualsegmentsareilluminatedbyconnectingtheindividualCathodeterminalstoa"LOW",logic"0"signal.a~g=0on,a~g=1off(ActiveLow)TheCommonCathodeDisplay(CCD)AllthecathodeconnectionsoftheLED'sarejoinedtogethertologic"0"orground.Theindividualsegmentsareilluminatedbyapplicationofa"HIGH",logic"1"signaltotheindividualAnodeterminals.a~g=1on,a~g=0off(ActiveHigh)Chapter425BCD-to-SevenSegmentDecoderTruthTableforBCD-to-Seven-SegmentDecoderChapter426AboutLCDDrivingChapter427EncoderEncodera1am……F1F2Fn……a2n

£m

£2nEncoding-theoppositeofdecoding-theconversionofanm-bitinputcodetoan-bitoutputcodewithn

£m

£2nsuchthateachvalidcodewordproducesauniqueoutputcodeCircuitsthatperformencodingarecalledencodersTypes:InstructionEncoderBinary-to-DecimalEncoderPriorityEncoder(widelyusedincomputerpriorityinterruptsystemandkeyboardcodingsystem)cypherEncoderChapter428MonitorWhat’sthebitwidthofdata?？01234567WorkpieceEncoderWorkpieceChapter429EncoderExampleAdecimal-to-BCDencoderInputs:10bitscorrespondingtodecimaldigits0through9,(D0,…,D9)Outputs:4bitswithBCDcodesFunction:IfinputbitDiisa1,thentheoutput(A3,A2,A1,A0)istheBCDcodefori,Chapter430EncoderExample(continued)Thetruthtablecouldbeformed,butalternatively,theequationsforeachofthefouroutputscanbeobtaineddirectly.BCDEquations:A2=D4+D5+D6+D7A1=D2+D3+D6+D7A0=D1+D3+D5+D7Chapter431PriorityEncoderTheaboveencoderdoesnotworkwhentheinputsignalcontainsmultiple“1”s.Oneencoderthatcanacceptallpossiblecombinationsofinputvaluesandproduceameaningfulresultisapriorityencoder.Amongthe1sthatappear,itselectsthemostsignificantinputposition(ortheleastsignificantinputposition)containinga1andrespondswiththecorrespondingbinarycodeforthatposition.Chapter432PriorityEncoderExamplePriorityencoderwith5inputs(D4,D3,D2,D1,D0)-highestprioritytomostsignificant1present-CodeoutputsA2,A1,A0andVwhereVindicatesatleastone1present.Xsininputpartoftablerepresent0or1;thustableentriescorrespondtoproducttermsinsteadofminterms.Thecolumnontheleftshowsthatall32mintermsarepresentintheproducttermsinthetableNo.ofMin-terms/RowInputsOutputsD4D3D2D1D0A2A1A0V100000XXX0100001000120001X00114001XX0101801XXX0111161XXXX1001Chapter433PriorityEncoderExample(continued)CoulduseaK-maptogetequations,butcanbereaddirectlyfromtableandmanuallyoptimizedifcareful:Chapter434SelectingofdataorinformationisacriticalfunctionindigitalsystemsandcomputersCircuitsthatperformselectinghave:AsetofinformationinputsfromwhichtheselectionismadeAsingleoutputAsetofcontrollinesformakingtheselectionLogiccircuitsthatperformselectingarecalledmultiplexersSelectingcanalsobedonebythree-statelogicortransmissiongatesSelectingCircuitYDBUSCBUSChapter435MultiplexersAmultiplexerselectsinformationfromaninputlineanddirectstheinformationtoanoutputlineAtypicalmultiplexerhasncontrolinputs(Sn-1,…S0)calledselectioninputs,2ninformationinputs(I2n

-1,…I0),andoneoutputYAmultiplexercanbedesignedtohaveminformationinputswithm<2naswellasnselectioninputsChapter4362-to-1-LineMultiplexerSince2=21,n=1ThesingleselectionvariableShastwovalues:S=0selectsinputI0S=1selectsinputI1Theequation:Y=I0+SI1Thecircuit:SChapter4372-to-1-LineMultiplexer(continued)Notetheregionsofthemultiplexercircuitshown:1-to-2-lineD