pld应用程序举例

library

PLDuseieee.std_logic_1164.all;entityduanmaisport(fff:outbit_vector(1to5);aaa:outbit_vector(1to5));architecturekkofduanmaisfff(1toaaa(1toPLDlibraryuseieee.std_logic_1164.all;entityjwisport(in1,in2:inintegerrange0to15;architectureggofjwsignalhe:integerrange0towithhe"0110000"when1|11|21|31|41,"1101101"when"1111001"when"0110011"when"1011011"when"1011111"when"1110000"when"1111111"when"1111011"when"0000000"whenothers;withheselectb<="0000000"when0<=heandhe<=9,else"0110000"when10<=heand"1101101"when20<=heand"1111001"when30<=heand"0110011"when40<=heand"0000000"whenothers;PLDlibraryuseieee.std_logic_1164.all;entityguozi3isport(in1,in2:instd_logic_vector(1to4);a,b:outstd_logic_vector(1to8));architectureggofguozi3iswithin1select"0110000"when"1101101"when"1111001"when"0110011"when"1011011"when"1011111"when"1110000"when"1111111"when"1111011"when"0000000"whenothers;within2selectb<="0110000"when"0001","1101101"when"1111001"when"0110011"when"1011011"when"1011111"when"1110000"when"1111111"when"1111011"when"0000000"whenothers;PLD顺序语句编程(0加到libraryuseieee.std_logic_1164.all;entityjinchenisport(in1:instd_logic;a:outstd_logic_vector(1toarchitectureggofjinchenissignalss:integerrange0to9;waituntilin1='1';ifss=10thenendendprocess;withssselecta<="1111110"when"0110000"when"1101101"when"1111001"when"0110011"when"1011011"when"1011111"when"1110000"when"1111111"when"1111011"when"0000000"whenothers;PLD矢 10个控制2个数码libraryuseieee.std_logic_1164.all;entitykongzhi2isport(a:outbit_vector(1to7); bit_vector(1to10));architectureffofkongzhi2isa<="1111110"whenb="1000000000"else"0110000"when "1101101"when"1111001"when"0110011"when"1011011"when"1011111"when"1110000"when"1111111"when"1110011"whenPLD晶振50Mlibraryuseieee.std_logic_1164.all;entityjinzhengisport(in50m:instd_logic;a:outstd_logic_vector(1to7));architectureggofjinzhengissignalin1:std_logic;signalss:integerrange0tosignalcount:integerrange0to25000000;in1<=notin1;endif;endwaituntilin1='1';ifss=10thenendendprocess;withssselecta<="1111110"when"0110000"when"1101101"when"1111001"when"0110011"when"1011011"when"1011111"when"1110000"when"1111111"when"1111011"when"0000000"whenPLD晶振50M自动跳变程序（0到libraryuseieee.std_logic_1164.all;entityjiadxxisport(in50m:instd_logic;a,b:outstd_logic_vector(1to7));architectureggofjiadxxissignalin1:std_logic;signalt,g:integerrange0tosignalcount:integerrange0to5925000000;in1<=notin1;endif;endwaituntilin1='1';ifg=9 ifg=5thenift=5endif;endendprocess;withga<="1111110"when"0110000"when"1101101"when"1111001"when"0110011"when"1011011"when"1011111"when"1110000"when"1111111"when"1111011"when"0000000"whenothers;withtselectb<="1111110"when"0110000"when"1101101"when"1111001"when"0110011"when"1011011"when"1011111"when"1110000"when"1111111"when"1111011"when"0000000"whenothers;PLD（1-8数码管显示）第六个显示libraryuseieee.std_logic_1164.all;entityjiadxxisport(a:outstd_logic_vector(1to7);b:outstd_logic_vector(1to3)); --显示的数 --显示的位“第6位PLD动态间隔1libraryuseentityjiadxxisport(in50m:instd_logic;b:outstd_logic_vector(1to3);a:outstd_logic_vector(1to7));architectureggofjiadxx count:integerrange0tosignalcount_one:integerrange0to1;signalone_hz:std_logic;one_hz<=notone_hz;endif;endwaituntilone_hz='1';ifcount_one=0thenendendPLD动态显示 libraryuseentitydz1121isport(in50m:instd_logic;a:outstd_logic_vector(1to7);b:outstd_logic_vector(1to3));architectureggofningyiissignalin1:std_logic;signalcount_c:integerrange0tosignalcount:integerrange0to2500;ifcount=2500in1<=notin1;endif;endwaituntilin1='1';ifcount_c=1thenendif;endprocess; count_cselecta<="1111110"when0,"0110000"when"0000000"whenwithcount_cselectb<="000"when0,"001"when"111"whenothers;PLD数码管显示libraryuseentityxian0-7isport(in50m:instd_logic;a:outstd_logic_vector(1to7);b:outstd_logic_vector(1to3));architectureggofxian0-7issignalin1:std_logic;signalcount_c:integerrange0tosignalcount:integerrange0to2500;waituntilifcount=2500thenin1<=notin1;endendwaituntilin1='1';casecount_cwhen whenwhenwhenwhenwhenwhenwhenifcount_c=7thenendif;endcase;endprocess;library

PLDuseieee.std_logic_1164.all;entityshizonisport(in50m:std_logic;a:outstd_logic_vector(1to7);--b:outstd_logic_vector(1to3));--architectureffofshizonsignalcount:integerrange0to250;--整数定signalcount_s:integerrange0to25000;--半signalg1,g2,s1,s2,b1,b2:std_logic_vector(1to7);--变量范围signalone_hz:std_logic;--定义1signalsignalx:integerrange0to7;-signalgg1,gg2,ss1,ss2,bb1,bb2:integerrange0to9;ifcount=250one_hz<=notone_hz;endif;endwaituntilin50m='1';ifcount_s=25000thenone_s<=notone_s;endif;endwaituntilone_hz='1';casexwhenwhenwhen2=>b<="010";whenwhen4=>b<="100";a<=s2;when5=>b<="101";whenwhen7=>b<="111";endcase;endprocess;waituntilone_s='1';ifgg1=9thenifgg2=5thenifss1=9thenifss2=5thenifbb1=9thenendif;ifbb1=3andbb2=2thenendif;endif;endendif;endendwithgg1selectg1<="1111110"when"0110000"when"1101101"when"1111001"when"0110011"when"1011011"when"1011111"when"1110000"when"1111111"when"1111011"when"0000000"whenothers;withgg2selectg2<="1111110"when0,"0110000"when"1101101"when"1111001"when"0110011"when"1011011"when"0000000"whenothers;withss1selects1<="1111110"when0,"0110000"when"1101101"when"1111001"when"0110011"when"1011011"when"1011111"when"1110000"when"1111111"when"1111011"when"0000000"whenothers;withss2selects2<="1111110"when0,"0110000"when"1101101"when"1111001"when"0110011"when"1011011"when"0000000"whenwithbb1selectb1<="1111110"when"0110000"when"1101101"when"1111001"when"0110011"when"1011011"when"1011111"when"1110000"when"1111111"when"1111011"when"0000000"whenothers;withbb2selectb2<="1111110"when0,"0110000"when"1101101"when"0000000"whenPLD单个音符编程 低2音libraryieee;useentityypyyisport(in50m:instd_logic;a:outarchitectureggofypyyissignalin1:std_logic;signalcount:integerrange0to25000000;ifcount=85034thenin1<=notin1;endendprocess;PLDlibraryuseentityypyyisport(in50m:instd_logic;a:outarchitectureggofypyyissignalin1:std_logic;signalin2:std_logic;signalcount:integerrange0tosignalcount_1:integerrange0tosignalys1s:integerrange0tosignaljia1:integerrange0to1;waituntilifcount=85034thenin1<=notin1;endendwaituntilin50m='1';ifcount_1=63775thenin2<=notin2;endendwaituntilin50m='1';ifys1s=50000000endif;ifjia1=0thenendif;endprocess;PLD1-7音符编程（if语句libraryuseentityypyyisport(in50m:instd_logic;a:outarchitectureggofypyyissignalin1:std_logic;signalin2:std_logic;signalin3:std_logic;signalin4:std_logic;signalin5:std_logic;signalin6:std_logic;signalsignalcount:integerrange0tosignalcount_1:integerrange0tosignalcount_2:integerrange0tosigna