数字电路与逻辑设计 课件 （陈彦辉）11-13 数字系统设计

数字系统设计 1

片上微控制系统原理与项目设计第十一讲授课内容数字系统设计处理数字滤波器控制微处理器设计电路，计算N！数字系统设计核心是自顶向下的设计思想和模块化的设计方法：（1）模块划分，即系统应该被划分为几个模块；（2）模块互联，即各个模块间的连接接口如何规划；（3）模块通信，即各个模块之间的数据如何交互。（1）试凑法把系统的总体方案分成若干个相对独立的功能部件，然后用组合逻辑电路和时序逻辑电路的设计方法分别设计并构成这些功能部件，最后把这些已经确定的部件按要求拼接组合起来，便构成完整的数字系统。（2）自上而下法把较大规模的数字系统从逻辑上划分为控制器和受控制器电路两大部分，采用逻辑流程图或其他工具来描述控制器的控制过程，并根据控制器及受控制器的逻辑功能，选择适当功能器件来实现。某简单的小型数字系统的功能要求如下：有4×4矩阵数字键盘和一行5个数码管。每个按键上标有一位十六进制数符，十六个按键标注不同值。每按一次键，相应的十六进制数符就显示在最右边的数码管上，以前显示的数符都向左移一个数码管。需求可以分解为三个基本子功能部分：数码管的动态显示矩阵键盘的按键检测数据移位保存数据处理基本模块输入输出逻辑结构功能描述真值表硬件描述波形图电路内部结构加工流程流程描述处理流程图流程变形按照模块功能改变流程图流程结构根据流程图用模块构建获取加工显示数据处理运算流控算术逻辑比较编码译码变换选择分配保存寄存存储运算模块算术运算

ABF逻辑运算

AF

比较运算

ABSA>BSA=BSA<B双目运算单目运算变换模块编码

I0IN-1译码D……

Y0YN-1D……M<<N压缩去压缩N维稀疏空间M维稠密空间N维稀疏空间第几种情况流控模块选择

D0DN-1分配YC……

Y0YN-1D……选来源选去处Cif(C==0)Y=D0;elseif(C==1)Y=D1;elseif()

⁝elseY=DN-1;if(C==0){Y0=D;Y1=×;…;YN-1=×;}elseif(C==1)){Y0=×;Y1=D;…;YN-1=×;}elseif()

⁝else{Y0=×;Y1=×;…;YN-1=D;}保存模块寄存

D存储Q

A0AN-1WR……不触发时保持原值存数据CPD0DM-1…RD取数据地址线入数据线写使能读使能…读写同时读写分时一组数据大量数据s=f(s,…);x[k]=;=f(x[k],…)A0AN-1WR……DI0DIM-1…RD…DO0DOM-1……出数据线双向数据线读写同时流程分析

ABFABFABF123N…si=2s=1i>Ns=s+ii=i+1假初始化

ΣΣΣ保存i保存s比较循环体节奏时钟触发真流程变形

i=2s=1i>Ns=s+ii=i+1假i=2s=1i>Ns=s+ii=i+1真s=si=i假条件不成立时，s和i值保持原值真要做的操作一直存在，只是是否使用流程变形

初始化与循环时，s和i值赋值不同i=2s=1i>Ns=s+ii=i+1真s=si=i假s=1i=2i>Ns=s+ii=i+1假s=si=i真初始否真假不同条件下选择不同结果所有操作都在流程逻辑结构s=1i=2i>Ns=s+ii=i+1假s=si=i真初始否假真

初始控制节奏控制输入参数DQCPABΣF1iDQCPsD0D1YCABΣFD0D1YCABSA<BND1D0YCD1D0YC21CPR流程逻辑结构DQCPABΣF1iDQCPsD0D1YCABΣFD0D1YCABSA<BND1D0YCD1D0YC21CPRds=1di=2i>Nds=s+idi=i+1s=dsi=di假ds=sdi=i真初始否假真

dsdi组合逻辑记忆时序逻辑数字系统RTL设计方法1、系统状态转移图描述。（与普通的状态转移图相比，转移条件不仅仅是某些输入输出比特）2、设计数据通路3、将数据通路与一个控制器相连4、将系统状态转移图描述转换为模块状态转移图。（把操作换成控制信号的输出。）（2）自上而下法把较大规模的数字系统从逻辑上划分为控制器和受控制器电路两大部分，采用逻辑流程图或其他工具来描述控制器的控制过程，并根据控制器及受控制器的逻辑功能，选择适当功能器件来实现。【例】饮料贩卖机。输入硬币，c检测信号，是否有硬币投入。a为投入钱币面值信息:1元面值。每瓶饮料的价格s为2元，得控制输出，控制饮料掉落。①系统状态图定义变量tot，累计现有钱数•初始化状态：设置d=0，tot=0•等待状态：等待硬币 –如果看到硬币，请转到添加状态•添加状态：更新总值：tot=tot

+a –存储当前硬币的价值，返回等待状态 –在等待状态下，如果tot>=s，请转到分配•分配状态：设置d=1（分配饮料） –返回初始化状态多位（数据）输入a和s本地注册数据操作tot=0，tot<s，tot=tot+a。

设计数据通路需要寄存器tot需要8位比较器比较S和TOT需要8位加法器执行tot=tot+a连接各模快控制输入/输出，定义信号名称

将数据通路与一个控制器相连控制器的输入 –外部输入c

（检测到硬币） –来自数据路径的输入

比较器输出，命名的tot_lt_s•控制器输出 –外部输出d（分配饮料） –控制输出tot_ld,tot_clr

转换为模块状态转移图

状态和转移不变

读写控制单元信号【例】基于激光的距离测量仪输入输出：B控制开关L激活激光S激光接收器D16比特距离数据创建初始状态，将其命名为S0–将激光初始化为关闭（L=0）–将显示的距离初始化为0（D=0）添加另一个状态，称为S1，等待按钮按下–B'–留在S1，继续等待–B–转到新状态S2问：S2应该做什幺？答：打开激光添加打开激光的状态S2（L=1）在状态S3中关闭激光（L=0）问：下一步做什幺？答：启动定时器，等待反射检测到反射（S）后，进入新状态S4–计算距离–假设时钟频率为3x108，DCTR保存米数，因此D=DCTR/2•S4之后，返回S1再次等待按钮2、设计数据通路数据通路数据存储数据计算看系统状态机，三个子步骤（a）使数据输入/输出成为数据路径输入/输出（b）将声明的寄存器实例化到数据路径（同时为每个实例化一个寄存器数据输出）（c）审查每一种状态和转移，以及实例化数据路径模块和用于实现任何数据的计算【例】总线接口–主处理器可以读取任何外设寄存器 •每个寄存器都有唯一的4位地址 •假设1个寄存器/外设。–设置rd=1，A=地址–在32位D线上寄存器数据 •硬件地址Faddr输入（可能来自DIP开关或他寄存器）步骤1：创建高级状态机–状态等待•在D上输出“无”（“Z”），将外设的寄存器值Q存储到本地寄存器Q1•等到看到此外设的地址（A=Faddr）且rd=1–状态发送数据•将Q1输出到D上，等待rd=0（表示主处理器已完成读取D）【例】视频压缩【例】数字滤波器数字系统设计

--简易处理器设计片上微控制系统原理与项目设计第十二讲授课内容数字系统设计处理数字滤波器控制微处理器设计处理器电路，计算N！55IntroductionProgrammable(general-purpose)processorMass-produced,thenprogrammedtoimplementdifferentprocessingtasksWell-knowncommonprogrammableprocessors:Pentium,Sun’sSpareOtherprogrammableprocessors:ARM,MIPS,8051,PIC,PowerPCLow-costembeddedprocessorsfoundincellphones,blinkingshoes,etc.HowtodesignasimpleprogrammableprocessorusingdigitaldesignmethodsRealprocessorscanbemuchmorecomplex8.1Seatbeltwarninglightsingle-purposeprocessor2x4e2310c0c1c2xt1regxt0xt2++***x(t)x(t-1)x(t-2)InstructionmemoryControllerPCIRRegisterfileRFDatamemoryDALUn-bit2x1Therepresentationoftheprocessingtaskinthememoryisknownasaprogram3-tapFIRfiltersingle-purposeprocessorGeneral-purposeprocessoraControlunitDatapath56BasicArchitectureProgrammableprocessorconsistsoftwomainparts:AdatapathAcontrolunitProcessinggenerallyconsistsof:LoadingsomedataTransformingthatdataTransformationstakeplaceinsideaprocessor’sdatapath.StoringthatdataBasicdatapath:UsefulcircuitinaprogrammableprocessorCanread/writedatamemory,wheremaindataexistsHasregisterfiletoholddatalocallyHasALUtotransformlocaldata8.2RegisterfileRFDatamemoryDALUn-bit2x1BasicDatapath57BasicDatapathOperationsLoadoperation:LoaddatafromanylocationinthedatamemoryintoanyregisterintheRFALUoperation:TransformsdatabypassingoneortwoRFregistervaluesthroughALU,performingoperation(ADD,SUB,AND,OR,etc.),andwritingbackintoRF.

Storeoperation:Stores(writes)RFregistervaluebackintoanydatamemorylocationNote:EachoperationcanbedoneinoneclockcycleRegisterfileRFDatamemoryDALUn-bit2x1RegisterfileRFDatamemoryDALUn-bit2x1RegisterfileRFDatamemoryDALUn-bit2x1LoadoperationALUoperationStoreoperationa58UnderstandingDatapathOperationsQ:

Whichofthefollowingarevalidsingle-clock-cycleoperations

forgivendatapath?1.Copydatafromadatamemorylocationintoaregisterfilelocation.A:

YES–That'saloadoperation2.Readdatafromtwodatamemorylocationsintotworegisterfilelocations.A:

NO–readingmorethanonedatamemorylocationandwritingtomorethanoneregisterfilelocationarenotsupportedduringadatapathoperation.3.Adddatafromtwodatamemorylocationsandstoretheresultinaregisterfilelocation.A:

NO –Doesnotsupportreadingtwodatamemorylocationsduringanoperation –Doesnothaveconnectionsdirectlyfromthedatamemory4.Copydatafromoneregisterfilelocationtoanotherregisterfilelocation.A:

YES–Why?5.Subtractdatainaregisterfilelocationfromadatamemorylocation,storingtheresultinaregisterfilelocation.A:

NO–Valuesreadfromdatamemorymustbeloadedintotheregisterfilefirst.a59BasicDatapathOperationsQ:Whicharevalidsingle-cycleoperations

forgivendatapath?MoveD[1]toRF[1](i.e.,RF[1]=D[1])A:YES–That'saloadoperationStoreRF[1]toD[9]andstoreRF[2]toD[10]A:NO–RequirestwoseparatestoreoperationsAddD[0]plusD[1],storeresultinD[9]A:NO–ALUoperation(ADD)onlyworkswithRF.Requirestwoloadoperations(e.g.,RF[0]=D[0];RF[1]=D[1],anALUoperation(e.g.,RF[2]=RF[0]+RF[1]),andastoreoperation(e.g.,D[9]=RF[2])RegisterfileRFDatamemoryDALUn-bit2x1RegisterfileRFDatamemoryDALUn-bit2x1RegisterfileRFDatamemoryDALUn-bit2x1LoadoperationALUoperationStoreoperationaQ&A6061BasicArchitecture–ControlUnitSupposethebasicdatapathshouldperformthesimpleprocessingtaskofaddingdatamemorylocation0anddatamemorylocation1together,andwritingtheresultindatamemorylocation9.ComputingD[9]=D[0]+D[1]Thisprocessingtaskcanbeachievedby“instructing”thedatapathtoperformthefollowingoperations:Loaddatapathmemorylocation0toregisterRF[0](i.e.,RF[0]=D[0])Loaddatapathmemorylocation1toregisterRF[1](i.e.,RF[1]=D[1])PerformanALUoperationthataddsRF[0]andRF[1]andwritestheresultbackintoRF[2](i.e.,RF[2]=RF[0]+RF[1])StoreRF[2]intodatamemorylocation9(i.e.,D[9]=RF[2]).D[9]=D[0]+D[1]–requiresasequenceoffourdatapathoperations:0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]a62BasicArchitecture–ControlUnitD[9]=D[0]+D[1]–requiresasequenceoffourdatapathoperations:0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]Eachoperationisaninstruction

Sequenceofinstructions–programLookscumbersome,butthat'stheworldofprogrammableprocessors–Decomposingdesiredcomputationsintoprocessor-supportedoperationsStoreprograminInstructionmemoryControlunitreadseachinstructionandexecutesitonthedatapathPC(Programcounter)–addressofcurrentinstructionIR(Instructionregister)–currentinstructionRegisterfileRFDatamemoryDALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]asignalstocontrolthedatapath63BasicArchitecture–ControlUnitTocarryout

eachinstruction,thecontrolunitmustperform3stagesrepeatedly:Fetch–Readinstructionfrominst.mem.Decode–DeterminetheoperationandoperandsoftheinstructionExecute–Carryouttheinstruction'soperationusingthedatapathaRF[0]=D[0]0->1R[0]:??

99"load"InstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2](a)FetchRF[0]=D[0]InstructionmemoryIControlunitPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]1(b)ControllerDecodeRegisterfileRFDatamemoryDD[0]:99ALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]RF[0]=D[0]1(c)Executesignalstocontrolthedatapath64BasicArchitecture–ControlUnitaRF[1]=D[1}1->2R[1]:??

102"load"InstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2](a)FetchRF[1]=D[1]InstructionmemoryIControlunitPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]2(b)ControllerDecodeRegisterfileRFDatamemoryDD[1]:102ALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]RF[1]=D[1]2(c)ExecutesignalstocontrolthedatapathTocarryouteachinstruction,thecontrolunitmustperform3stagesrepeatedly:Fetch–Readinstructionfrominst.mem.Decode–DeterminetheoperationandoperandsoftheinstructionExecute–Carryouttheinstruction'soperationusingthedatapath65BasicArchitecture–ControlUnitaRF[2]=RF[0]+RF[1]2->3R[2]:??

201"ALU(add)"InstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2](a)FetchRF[2]=RF[0]+RF[1]InstructionmemoryIControlunitPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]3(b)ControllerDecodeRegisterfileRFDatamemoryDALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]RF[2]=RF[0]+RF[1]3(c)Execute99102201signalstocontrolthedatapathTocarryouteachinstruction,thecontrolunitmustperform3stagesrepeatedly:Fetch–Readinstructionfrominst.mem.Decode–DeterminetheoperationandoperandsoftheinstructionExecute–Carryouttheinstruction'soperationusingthedatapath66BasicArchitecture–ControlUnitaD[9]=RF[2]3->4R[2]:201"store"InstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2](a)FetchD[9]=RF[2]InstructionmemoryIControlunitPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]4(b)ControllerDecodeRegisterfileRFDatamemoryDALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]D[9]=RF[2]4(c)ExecuteD[9]=??201signalstocontrolthedatapathTocarryouteachinstruction,thecontrolunitmustperform3stagesrepeatedly:Fetch–Readinstructionfrominst.mem.Decode–DeterminetheoperationandoperandsoftheinstructionExecute–Carryouttheinstruction'soperationusingthedatapath67BasicArchitecture–ControlUnitRegisterfileRFDatamemoryDALUn-bit2x1DatapathInstructionmemoryIControlunitControllerPCIR0:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]signalstocontrolthedatapathControllerFSM68Example:CreatingaSimpleSequenceofInstructionsQ:Createasetofinstructions(orsequence)tocomputeD[3]=D[0]+D[1]+D[2]onearlier-introducedprocessor.A1:OnepossiblesequenceFirstloaddatamemorylocationsintoregisterfileR[3]=D[0]R[4]=D[1]R[2]=D[2](Notearbitraryregisterlocations)Next,performtheadditionsR[1]=R[3]+R[4]R[1]=R[1]+R[2]Finally,storeresultD[3]=R[1]aA2:AlternativesequenceFirstloadD[0]andD[1]andaddthemR[1]=D[0]R[2]=D[1]R[1]=R[1]+R[2]Next,loadD[2]andaddR[2]=D[2]R[1]=R[1]+R[2]aFinally,storeresultD[3]=R[1]Sixinstructionswouldappearininstructionmemorylocations0through569Example:EvaluatingtheNumberofCyclestoExecuteaProgramQ:Howmanycyclesareneededtoexecutesixinstructionsusingtheearlier-describedprocessor?A:Eachinstructionrequires3cycles:1cycletofetchtheinstruction,1cycletodecodethefetchedinstruction,and1toexecutetheinstruction.At3cyclesperinstruction,thetotalcyclesfor6instructionsis6instr*3cycles/instr=18cyclesaThree-InstructionProgrammableProcessorInstructionSet–ListofallowableinstructionsandtheirrepresentationinmemoryReserveacertainnumberofbitsintheinstructiontodenotewhatoperationtoperformRemainingbitsspecifyadditionalinformationneededtoperformtheoperationsuchastheaddressesoftheregistersthatareinvolvedintheoperationThree16bitswideinstructions,leftmost4bitsidentifytheoperation,andtheremaining12bitsidentifytheregisterfileanddatamemoryaddresses:8.3bit11bit10bit9bit8bit7bit6bit5bit4bit3bit2bit1bit0Operationcode0000:Load0001:Store0010:AddAdditionalinformationbit15bit14bit13bit12Three-InstructionProgrammableProcessorThree16bitswideinstructions,e.g.,Loadinstruction —0000r3r2r1r0

d7d6d5d4d3d2d1d0Storeinstruction —0001r3r2r1r0d7d6d5d4d3d2d1d0Addinstruction —0010ra3ra2ra1ra0

rb3rb2rb1rb0rc3rc2rc1rc0718.3InstructionmemoryI0:00000000000000001:00000001000000012:00100010000000013:00010010000010010:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2}DesiredprogramaopcodeoperandsInstructionsin0sand1s–machinecodeaExample:ProgramforThree-InstructionProcessor72RegisterfileRFDatamemoryDALUn-bit2×1DatapathInstructionmemoryIControlunitControllerPCIRsignalstocontrolthedatapath0:00000000000000001:00000001000000012:00100010000000013:00010010000010010:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2}DesiredprogramComputesD[9]=D[0]+D[1]ThedesiredcomputationD[9]=D[0]+D[1]canbewrittenastheprogram:Example:ProgramforThree-InstructionProcessorWriteprogramstoperformthecomputationD[5]=D[5]+D[6]+D[7]usingtheabove-definedthreeinstructionset.73Loadinstruction—0000r3r2r1r0d7d6d5d4d3d2d1d0Storeinstruction—0001r3r2r1r0d7d6d5d4d3d2d1d0Addinstruction—0010ra3ra2ra1ra0rb3rb2rb1rb0rc3rc2rc1rc0Thenumberbeforethecolonrepresentstheinstruction’saddressintheinstructionmemory.Thetextfollowingthetwoforwardslashes“//”representsacomment,andisnotpartofaninstruction.MachineCodevs.AssemblyCodeAprogramrepresentedas0sand1sisknownasmachinecode.Wehumansarenotgoodatwritingandreadingprogramsas0sand1sCan’tunderstandthose0sand1seasilyWillmakeplentyofmistakeswhenwritingsuchprogramsThus,earlycomputerprogrammersdevelopedatoolknownasanassembler(whichitselfisjustanotherprogram)tohelphumanswriteprograms.Allowsustowriteinstructionsusingmnemonics(助记符),orsymbolsAssemblerautomaticallytranslatestomachinecode74AssemblyCodeMachinecode(0sand1s)hardtoworkwithAssemblycode–Usesmnemonics(助记符)Loadinstruction—MOVRa,dspecifiestheoperationRF[a]=D[d].amustbe0,1,...,or15—soR0meansRF[0],R1meansRF[1],etc.dmustbe0,1,...,255•Storeinstruction—MOVd,RaspecifiestheoperationD[d]=RF[a]•Addinstruction—ADDRa,Rb,RcspecifiestheoperationRF[a]=RF[b]+RF[c]750:MOVR0,01:MOVR1,12:ADDR2,R0,R13:MOV9,R20:RF[0]=D[0]1:RF[1]=D[1]2:RF[2]=RF[0]+RF[1]3:D[9]=RF[2]Desiredprogram0:00000000000000001:00000001000000012:00100010000000013:0001001000001001machinecodeassemblycodeTheprogramwrittenusingmnemonicsismucheasiertounderstandthanthe0sand1s,andthatwillbetranslatedtomachinecodebyanassembler(assemblycode).Control-UnitandDatapathforThree-InstructionProcessorTodesignacompletedigitalcircuitforathree-instructionprogrammableprocessor,wecanbeginwithahigh-levelstatemachinedescriptionoftheprocessor'sbehavior76StoreD[d]=RF[ra]op=0001LoadRF[ra]=D[d]op=0000DecodeFetchIR=I[PC]PC=PC+1InitPC=0AddRF[ra]=RF[rb]+RF[rc]op=0010opmeansIR[15..12]rameansIR[11..8]rbmeansIR[7..4]rcmeansIR[3..0]dmeansIR[7..0]executestates简易处理器设计Control-UnitandDatapathforThree-InstructionProcessorCreatedetailedconnectionsamongcomponents78FetchDecodeInitPC=0StoreIR=I[PC]PC=PC+1LoadAddRF[ra]=RF[rb]+RF[rc]D[d]=RF[ra]RF[ra]=D[d]op=0000op=0001op=0010PCclrup16I_rdPC_incIRId1616R_ldIdatardaddrControllerControlunitDatapathRF_W_wrRF_Rp_addrRF_Rq_addrRF_Rq_rdRF_Rp_rdRF_W_addrD_addr8D_rdD_wrRF_salu_s0addrDrdwr256x1616x16RF16-bit2x1W_dataR_dataRp_dataRq_dataW_dataW_addrW_wrRp_addrRp_rdRq_addrRq_rd0161616161616s1ABs0ALU444PC_clrAssumethat:alu_s0=1,ALUaddsitsinputsalu_s0=0,ALUpassesinputARF_sistheselectlineforthe2x1muxDatamemoryRefineddatapathandcontrolunitforthethree-instructionprocessorInstructionmemoryControl-UnitandDatapathforThree-InstructionProcessorConverthigh-levelstatemachinedescriptionofentireprocessortoFSMdescriptionofcontrollerthatusesdatapathandothercomponentstoachievesamebehavior79FetchDecodeInitPC=0PC_clr=1StoreIR=I[PC]PC=PC+1I_rd=1PC_inc=1IR_ld=1LoadAddRF[ra]=RF[rb]+RF[rc]D[d]=RF[ra]RF[ra]=D[d]op=0000op=0001op=0010D_addr=dD_wr=1RF_s=XRF_Rp_addr=raRF_Rp_rd=1RF_Rp_addr=rbRF_Rp_rd=1RF_s=0RF_Rq_addr=rcRF_Rq_rd=1RF_W_addr=raRF_W_wr=1alu_s0=1D_addr=dD_rd=1RF_s=1RF_W_addr=raRF_W_wr=1aASix-InstructionProgrammableProcessorLet'saddthreemoreinstructions:Load-constantinstruction—0011r3r2r1r0c7c6c5c4c3c2c1c0MOVRa,#c—specifiestheoperationRF[a]=cSubtractinstruction—0100ra3ra2ra1ra0rb3rb2rb1rb0rc3rc2rc1rc0SUBRa,Rb,Rc—specifiestheoperationRF[a]=RF[b]–RF[c]Jump-if-zeroinstruction—0101ra3ra2ra1ra0o7o6o5o4o3o2o1o0JMPZRa,offset—specifiestheoperationPC=PC+offsetifRF[a]is0808.4ExtendingtheControl-UnitandDatapath811:TheloadconstantinstructionrequiresthattheregisterfilebeabletoloaddatafromIR[7..0],inadditiontodatafromdatamemoryortheALUoutput.Thus,wewidentheregisterfile’smultiplexerfrom2x1to3x1,addanothermuxcontrolsignal,andalsocreateanewsignalcomingfromthecontrollerlabeledRF_W_data,whichwillconnectwithIR[7..0].(shownaslabeled1)2:ThesubtractinstructionrequiresthatweuseanALUcapableofsubtraction,soweaddanotherALUcontrolsignal.(shownaslabeled2)3:Thejump-if-zeroinstructionrequiresthatwebeabletodetectifaregisteriszero,andthatwebeabletoaddIR[7..0]tothePC. 3a:Weinsertadatapathcomponenttodetectiftheregisterfile’sRpreadportisallzeros(thatcomponentwouldjustbeaNORgate).(shownaslabeled3a) 3b:WealsoupgradethePCregistersoitcanbeloadedwithPCplusIR[7..0].Theadderusedforthisalsosubtracts1fromthesum,tocompensateforthefactthattheFetchstatealreadyadded1tothePC.(shownaslabeled3b)DatapathRF_Rp_addrRF_Rq_addrRF_Rp_zeroRF_W_addrD_addrD_rdD_wrRF_s1RF_W_dataRF_s0alu_s1alu_s0addrDrdwr256x1616x16RF16-bit3x1W_dataR_dataRp_dataRq_dataW_dataW_addrW_wrRp_addrRp_rdRq_addrRq_rd0161616161616s1s012ABs1s0ALU4443a2=01188s1001s0010ALUoperationpassAthroughA+BA-BPCclrldup16IRId16datardaddrControllerControlunita+b-116**+3bIR[7..0]RF_W_wrRF_Rp_rdRF_Rq_rdExample:ProgramfortheSix-InstructionProcessorExampleprogram–Countnumberofnon-zerowordsinD[4]andD[5]Resultwillbeeither0,1,or2PutresultinD[9]82AssemblycodeCorrespondingmachinecodegeneratedbyanassemblerNote:Thespacesinthemachinecode’s16-bitinstructionsarethereforeaseofreadingbyus,actualmachinecodehasnosuchspaces.FurtherExtensionstotheProgrammableProcessorTypicalprocessorinstructionsetwillcontaindozensofdatamovement(e.g.,loads,stores),ALU(e.g.,add,sub),andflow-of-control(e.g.,jump)instructionsExtendingthecontrol-unit/datapathfollowssimilarlytopreviously-shownextensionsInput/outputextensionsCertainmemorylocationsmayactuallybeexternalpinse.g,D[240]mayrepresent8-bitinputI0,D[255]mayrepresent8-bitoutputP7838.5256x16DW_dataR_dataaddrrdwr0:1:2:239:240:241:248:255:00..000..0I0I1P0P7ProgramusingI/OExtensionsMicroprocessorsacommonchoicetoimplementadigitalsystemEasytoprogramCheap(aslowas$1)Availablenow84I3I4I5I6I7I2I1I0P3P4P5P6P7P2P1P0voidmain(){while(1){P0=I0&&!I1;//F=aand!b,}}0Fba101016:007:057:069:009:01timeDesiredmotion-at-nightdetectorProgrammedmicroprocessorCustomdesigneddigitalcircuitProgramUsingInput/OutputExtensionsUnderlyingassemblycodeforCexpressionI0&&!I1.850:MOVR0,240//moveD[240],whichisthevalueatpinI0,intoR01:MOVR1,241//moveD[241],whichisthatvalueatpinI1,intoR12:NOTR1,R1//compute!I1,assumingexistenceofacomplementinstruction3:ANDR0,R0,R1//computeI0&&!I1,assuminganANDinstruction4:MOV248,R0//moveresulttoD[248],whichispinP0256x16DW_dataR_dataaddrrdwr0:1:2:239:240:241:248:255:00..000..0I0I1P0P7voidmain(){while(1){P0=I0&&!I1;//F=aand!b,}}控制器设计思路控制器主要模块时序控制模块取指处理模块指令译码模块控制指令设计思路--时序控制每条指令的执行需要控制单元协调多个电路按照规程进行工作，每个电路所需要的控制信号需要在不同时间内生效。几种参考流程设计自己的控制流程控制指令设计思路--时序控制实现将一次操作采用三个时钟周期完成。第0个时钟上升沿锁存PC，第1个时钟内完成译指、取数和运算，第2个时钟完成存储器读或写以及输出寄存器锁存使能。在第3个时钟到来时，进行新一轮指令操作。电路主要信号的时序图时序控制模块还可以将译码的控制结果在指定时钟输出。

CLKmLEmWRmRDmLEmSLEnWRnRDLESLEPCLE功能↑0xxxx-----保持↑10xxx01001PC

PC+1↑110xx10001

↑1xx0x--101

↑1xxx0--011

PCLE：PC锁存使能LE：通用寄存器Rx锁存使能SLE：PSR锁存使能，nRD：输出存储器读取nWR：输出存储器载入parameterSI=2'b00,S0=2'b01,S1=2'b10,S2=2'b11;reg[1:0]state=SI;reg[1:0]next_state=S0;

always@(negedgeclk)begin//Thisisacombinationalalwaysblock//if(state==SI)//begin

//endcase(state)SI:next_state=2'b01;S0:next_state=S1;S1:next_state=S2;S2:next_state=S0;//Statetransitionlogicendcaseend

always@(posedgeclk)beginstate=next_state;end

assignnwr=!((state==S2)&&(!mwr));assignnrd=!((state==S2)&&(!mrd));assignle=(state==S2)&&(mle);assignsle=(state==S2)&&(msle);assignpcle=(state==S2);SIS0S1S2再看看指令通过改变处理电路中的信号取值可以实现不同的功能，这些信号取值按序排列构成的二进制数称为一条操作指令。不同的指令格式指令与字长的关系控制指令设计思路--取指PC输出作为指令存储器的地址输入，指令存储器进行片内译码来选择相应的指令存储单元并输出至指令数据总线ID上。指令锁存信号PCLE锁存当前总线上的指令代码并保存在IR中。功能表moduleInst