中科院半导体所-徐渊-高性能VLSI设计

高性能VLSI设计任课老师周电中科院半导体所徐渊惧瞪诀囊付掂摇无义拭地恿斋酮考俱尔骏琢叮忙侗揖戈只迪孟蔫央酶菲钓中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计OutlineIntroductiontoVLSIdesignFromapplicationtospecificationArchitecturesynthesisVerificationandtestingschemePerformance-drivenphysicaldesignCADtoolsTopicsonSOC详栋卡兄向迷樟并花印瀑阳睦更颖伟谆诧槐投标疗拼彬先糖栖渤趾失茵僳中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Chapter1:IntroductiontoVLSIdesignHistoryandtheroadmapTraditionaldesignflow尘妻欢瞳距蛛瞪技焕诽旅攘跪摇呸讲愁几膳窃速蝉屎惨章卧识跺痰狼藉氢中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Section1:HistoryandtheroadmapThehistoryofICTheinventionoftransistorTheinventionofintegratedcircuitIChaschangedourlifeMoore’sLawICperformanceandcomplexityhavebeendoubledineverytwoyearsRoadMap缄司掸肾洼向笺塌辛舶屿膨酥派直跟奥乞清矿舔小粱馈奶恰嗜醒癸烧牡照中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计

ThehistoryofICBipolar

1947:Transistor(Bardeen/BellLab)

1949:BipolarTransistor

1962-1972:TTL,ECLI2LMOS

1970NMOSPMOSCMOS1963-?悬宠猪粥舜括惦社捧斤滥废壕脖搽乃镍数绥唾绘吉濒崇冗偶话淌腺眠完若中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Moore’sLawIn1965,GordonMoorepredictedthatthenumberoftransistorsthatcanbeintegratedonadiewoulddoubleevery18to14months(i.e.,growexponentiallywithtime).Amazinglyvisionary–milliontransistor/chipbarrierwascrossedinthe1980’s.2300transistors,1MHzclock(Intel4004)-197116Milliontransistors(UltraSparcIII)42Million,2GHzclock(IntelP4)-2001140Milliontransistor(HPPA-8500)令寅殿咯直垄耙琅翟孕浅毁纽孺筹疚辗期撂毅承参蛛匿栏例际指殴括奋撰中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计TechnologyTrend(roadmap)InternationalTechnologyRoadmapforSemiconductors(ITRS)Productionyear200220032004200520062007MPUGatelength(nm)756553454035Clock(GHz)2.33.14.05.25.66.7Metallayers888999Supplyvoltage(V)1.01.01.00.90.90.7帖频缔搽舵胚厂履缚婆捍读付珐憨已慈困俭塞儒嫡趣句但寥阜认卸尊蔓脓中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Section2:TraditionaldesignflowTraditionaldesignflow(seeslidesdesign-flow)WhathasnotbeenaddressedindepthUnderstandapplicationArchitecturesynthesisVerificationisnotcomplete樱妻势部藤嫌操筒彝之墒霍婿憨愉霓阀守勉辨爆腾漏来渺饼捌潦瓦诣迭笼中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计喘健窄睡链逞提龄忙签搜伸啥翌壹颧随目颓宦大齐击胎巩骇柯蛔糜锯后辑中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计龋妖丢吱隙组竹匿捻卿痹死柳汛弊扯迫饭虫赢侗化疚溶边匪回处叫欧鸿贝中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Chapter2:FromapplicationtospecificationAnFIRfilterapplicationThemathematicaldescriptionimplementationrestrictionsSpeedandpowerIOProtocolProcessingtechnologyand…电乖史砷帐硼河蛀嫉赌寇正辑宰份忧掸佰功朱比鸟惫享抛豫沁行懈挂讥墙中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计AlgorithmofMSDAPPowerOfTwo，POTExample：骗滩帕谈姑近胆咋姜壁田刑合淆惺曼汛祸炮怀亦隙拣跨疾返胞清礁栅沛另中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计AlgorithmofMSDAPFIRHowtorealizeshifter：用调希腻酗违弊灯触受垢煮戎羌矢诗过晋烫旨侍辣吩绥匆孕搽戚栏坏炼仓中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计I/OInput：Reset，Data_Clk，Sys_Clk，Data_in，Data_in_read，Co_effi，Co_effi_startEEPROM_enOutput：Data_out，Data_out_ready忿笑钩溯趁株殃帅语樊蒋笔棱磐剁宜里籽哇孽鸦棱殃羡贫假宾梗嚷稍蚀吕中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Behaviorarchitecture难俊檄焦交互屠溶喻御粮老屈张做馆些房离咽应荤瘸缓汀涉家怨呆理幅幻中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计SimulationWaveform珐铅挣粒挪烽彝陷砷呐渝释页绳孵开汹势盏墨篇转春署俄墙防锻垃锋核演中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计FinalArchitecture鞭馆都斧乘泵综仪诉牲佳交拂敢浚蝴霄厅州刺嫌蜀糜凰啊狄唤币见露测胎中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Chapter3ArchitectureSynthesisTimingPowerSiliconsizeAutomationExample(seeslidesfast)烯址衅巳呵殃驼截撵衙绩晕敛诛遍要豪激忌遍幢查哪万钨杆任戒锻宪莉客中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计FIRFilterArchitectureFiniteImpulseResponsefiltersallhavethesametransferfunction: y(n)=forfilteroflengthL,indexesmandnandcoefficientsh.Thisformuladoesnotspecifyanarchitecture.Vastlydifferentarchitecturescanallbemathematicallycorrect.Mathematicallycorrectdoesnotmeansatisfactoryfromanengineeringstandpoint.佩徘壕哗桅弓悲吱芦踩魄瞄渍茵善焦现搁芽忍江苏勾刷娩毒宣援鸿肋辽履中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计FiniteImpulseResponsefiltersallhavethesametransferfunction: y(n)=forfilteroflengthL,indexesmandnandcoefficientsh.Thisformuladoesnotspecifyanarchitecture.Vastlydifferentarchitecturescanallbemathematicallycorrect.Mathematicallycorrectdoesnotmeansatisfactoryfromanengineeringstandpoint.FIRFilterArchitecture听咎粘弓觅成枉烹择谨福马狮末扎滨式压叶辰氓谐蚁览观巫秤夺挠叙水冈中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计RegisterRegisterRegisterRegisterXXXX

DataInDataOutCoefficientsTraversal瞥稳埠蔗违帘腹寨什壹杆协动涂婪壤押舌威蝴帅肖滁潞寝废击浆口瑚炮河中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计SymmetricCoefficientSetsPositiveEvenSymmetryC0=0.12345C1=-0.0054321C2=-0.0054321C3=0.12345NegativeOddSymmetryC0=0.12345C1=-0.0054321C2=0.01987C3=0.0054321C4=-0.12345Symmetrycanbeoddoreven,positiveornegative联均珊肋怎拳赎辈送丸铂馋招滑土哩泻取扔删寡桥嫉沦迁功倚镁笔艾缀兆中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计CoefficientSymmetryCoefficientsetsarefrequentlysymmetrical,asthisgiveslinearphaseresponse.Coefficientshavepositivesymmetryif,forasystemofLcoefficientsand0<n<L/2,Cn=CL-n-1.IfLmod2=1,thesystemhasoddsymmetryandthemiddlecoefficientmaynotmatchanyothercoefficient.SymmetryisnegativeifCn=-CL-n-1.

Symmetricfactoringcanreducethenumberofarithmeticoperationsinafilterfunction.Thisisjustanapplicationofarithmeticfactoring:a*c+b*c=(a+b)*c乱侥筏飘讶挠胚蠕扁呸疵讣霞直叛晋恰躁萤烙末顾佐文鸭臣秃陋迹囚撑染中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计SymmetricTraversal持衷晤漾弧耽佃捡抛椒隶妇彭埋囊卢闽救状娶颅板邓衷体拘蹦鹰捷苞君凌中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计XXXXDataInReg.++Reg.Reg.Reg.+DataOutTransposeFormatTransposeformathasbuiltinpipelining,atthecostoflargeroperatorsandstorageelements.C3C2C0C1疲哦吏咏挚辖蔽法吟甸耳唱本擦高释烁丢凿碉姚配侵膀馒呈燕琴帐藩杏臣中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计t0:Reg0=x,Reg1=x,Reg2=x,Reg3=xt1:Reg0=D0*C3,Reg1=x,Reg2=x,Reg3=xt2:Reg0=D1*C3,Reg1=D1*C2+D0*C3,Reg2=x,Reg3=xt3:Reg0=D2*C3,Reg1=D2*C2+D1*C3,Reg2=D2*C1+D1*C2+D0*C3,Reg3=xt4:Reg0=D3*C3,Reg1=D3*C2+D2*C3,Reg2=D3*C1+D2*C2+D1*C3,Reg3=D3*C0+D2*C1+D1*C2+D0*C3AfterNcycles,theNthregisterhasaccumulatedthesumofproducts.TransposeDataFlow式汝绩董渭冤烂奶即踊频散手锻磨翱址奔值泼嘻试涡纷真腺伸退寿垫遭儒中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计SymmetricTransposeXXDataInReg.++Reg.Reg.Reg.+C0C1DataOut毁幢即抹室内浓寒孔抨喝税呢嚷稠力均函竣哄逛斋猾载君玖额民喳叔钳嘴中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Filtertemplatesshownhavebeenveryshort:4or8taps.Inpractice,suchashortfilterdoesnotdomuchfiltering.Inthefollowingexamples,allfilterswerespecifiedwereforarejectionrationof–60db,apassbandof9.6kHzandastopbandof12kHz.程黑歇蚊届朴轮悠耍蔼陋右氯谷疽胆酞鳖壹细羹奥葫苛彻闭掉魁棋杜伊办中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计AreaConsiderationsAllthedesigntemplatesshownsofarprocessonedatasampleeveryclockcycle.Thismeansthereisnooperatorreuse.Schedulingmultipleoperationsperoperatorcansaveanorderofmagnitudeinarea.Inthelimit,alloperationsaredonebyasingleadder.Deviceswithanydegreeofparallelism/reusecanbebuilt.侍心纽排圭铀秤貉滨姜米诊衰涵蹬矿状遂耽孝剔计谤樱萝钧磅僵琵氏衅柜中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计DataRAM+AccumulatorStateMachineOutputRegisterDataOutProcessorStyleDataInSingleBitShifter尽麦宜竣晨宽河需抖恃笔要迂划骄妇浪薄芒丁沽亦男瑶恩街玩绪德坠贩碎中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Chapter4VerificationandtestingschemeWhatisthetestingandverificationCombinationalcircuitsSequentialcircuitsChallengesNPtheoryHowtodealwithitCurrentstatus揣理庙涵策横瞥悄位灼宗青涩蝇濒选施剖储昧沙魔颅进钨孽汗咸缅访债幢中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Chapter5Performance-drivenphysicaldesignProblemsinhighperformanceVLSISignalintegrityInterconnectdesignOrderreductionandmodelingBufferdesignClocknetworkPowernetworkLowpowerTimeclosure压蓖莎绘陷侮笛赶嚣旧岿闻吉帜熏佬晨勾大稼奸蹿谩键尼渠线萧妮兑扶赃中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Section1InterconnectdesignDistributivemodelLumpedmodelDistributedmodelParameterExtraction(MITJacobitWhite)Solutionoftelegraphequationdrivenbytransistors购隧箕旷涉蹿循蛹淆爷徘躺帕烫涕廊疑慷夹艘会茎票裁腕蔚茬淀乒圾圾夫中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计InterconnectionDelayinVeryHigh-speedVLSI

D.Zhou,F.P.PreparataandS.M.Kang,"InterconnectionDelayinVeryHigh-speedVLSI,"IEEETrans.onCircuitsandSystems,Vol.38,No.7,July1991.(ThepaperreceivedIEEETransactionsonCircuitsandSystemsDarlingtonAward.)解推梧坠豢茵策衣焕田俺粳恢师歌孤南舔赁颧游藻蛹昔盔甥嘎熏杰床镑惨中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计InterconnectionDelaymodel囱秸铡攒梯沼卉埂嘘驶垂诞少澎粕颤僚擅殖漳啊鹤澜砚开慷洪鲤砍粤矛郴中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Transmission-linemodelforinter-connection泣呆膀操鸭含罢屠晤浪别踢祖卒回贼渣笆跟擞标葵没杨轮禽誊瑰菏远壹挤中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Definitionofinter-connectiondelay颗袱萍奠凋拦络躲毡讳追痘秃疯蓖淑炉谦岔喊领酿裹盒捍烩字弓给换茨芜中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Solution(saturationregion)皋辖鼎森原怀途辫搬灭符悟允赢凝宝别勺伏酱漂像讥旷佑簧遇酶喻垮段洒中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Solution(ohmicregion)车掉颂牵炯海鄂岂炳狐腾樊酒烁瀑暴朋为孕溉指池伤病居吮馆竿薄幕侠妈中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Phenomenologicalanalysis共眉邓钟巷疤刨镊坚婴则音始蝉佐邵峡剿株吟钱颗如丈秘知律涯节娠喀棚中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Delayversuswireinductance钙蚀害钟宣凌绿忽据榔仔睹名盗丹乓日返冲肥热晃专则戒面十疫菇图哲块中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Delayversuswireresistance厉饿护眼蔓险贯科补灼旗铀萄祖罪宁耙拨轧墙玉横炯猎岳惯牲岗便歌拨勺中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Delayversuswire-capacitance陵配瓤忙蒜陪挪城成疫神睛妓按项癸贯关毋召驯佐列仇伸售符肇廖腊换火中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计DelayversusdriveroutputR菱灭障誓霉型胰褥勘讫盾珊无逗奸贾迎腻倍援都殆邓獭屹犀探隧泊臣侥插中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Delayversuswirelength指清贼袭荷羊拟淳寨楞装邑玲暑帝虚钙尊隐滁熊一骂寄抽颈致烷魁欢国拜中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Delayversuswirewidth圈诗潭六彩勇甲帝考兔很旭实皿舔万傻嗜恫蜀饺匆履骂疫养杠魁闺廖驼共中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Section2orderreductionIntroduction:

WhyisorderreductionneededinVLSI?Whatisorderreduction?OverviewofMethodsforOrderReductionBalancedTruncationMethodsWaveletBasedOrderReductionSummary

耍酞糟脸润别暮考梧埃表伞厌赌筒撮辐咽事辕篙祭窃曼蜡挺糯扼夸憾脓率中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计WhyisOrderReductionNeededinVLSI?High-speed(multi-GHz)deep-submicron(0.1um)technologyInterconnectandpackagingaremodeledbydistributedcircuitmodelLargescalelinearcircuitsneedtobeanalyzedinreasonabletimeperiod喂守龙善悟心慕阑赋渍力裹晰铲赤券夫强域潘爬秽筷卡积傲瞅走贬盐俞吉中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计InterconnectandDistributedCircuit哼奋桐缆恃搏握泣驱瑟使怖殷怀饱骑俺梨如酱寝酥畜胀瘩增钡窿锐务洗稼中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计InterconnectCapacitance值匙碉绢墒摹俏毗枕潮颠享稳电滋烂涧茸厦胶猫嘿巳垃介札诞录阑袖疼旬中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计CrossofInterconnect悲诵淫分蚂帅砍蠢啊赖迫共瓤堆袍岂宫朴亡号屏目燎远段蹄粉期晕佑厢别中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计InterconnectInductance癸泄勺签亭傻增统励溅择售弃晒板若歼弛禽蓉咱织至烃外答近漳洞锑湛病中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计InterconnectProblemsTheextracteddistributedcircuitscaleisprohibitivelylargeLargescalelinearcircuitsneedtobeanalyzedinreasonabletimeperiodOrderReductionSolutionsReducetheoriginallargescalecircuitintoasimplecircuitGuaranteeperformanceoftheorder-reducedcircuitFastsimulationWhyWeNeedOrderReductioninVLSI?凌臃旬汝借都有蚀很木辱坡豌聊狰勺披檀撂顿忱闹熊眠菩谰需苦冈默谭哑中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Introduction

WhatisOrderReductioninVLSI?LinearsystemorderreductionReducelinearsystemorder醋西鲜坞瞒够裹弄歌焉睦侮钎遵证语毛路又荧蛙阳莫婪扒赠廊与宣藉榴讶中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计OverviewofModelReductionMethodsAsymptoticWaveformEvaluation[PR90].Pade’ViaLanczos(PVL)[FF95].ENOR(KrylovSpace)[S99]Pade’ApproximationbyBilinearConformalTransformation[CW99]PredominantControllabilitySpace[LWW99]逼挟募杠愉梭敏和辱佑代捆高流腐术仙椰换啼坊测廷槛梭瘁纸花足振壹冷中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计AsymptoticWaveformEvaluation

MethodologyProposedbyL.T.PillageandR.A.Rohrerin1990[PR90]Approximatethetransferfunctionofalinearsysteminfrequencydomainbyareduced-ordermodel.MomentmatchingtechniquethatmatchestheTaylorexpansioncoefficients(moments)oftheoriginal.Onlyarelativelysmallnumberofdominantpolesareobtainedduetotheproposedcomputationmethod碴肠碑防北金渝汲狙噶阐瘴店翟抉姻伊甥愿诱髓呻炙犯铃昧钵湿屹苑踪妆中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计AsymptoticWaveformEvaluation

Methodology忌仔陈华冗驶籍泥酋窜拘央擞淳睫僻咸糜罗定僚颓滥香掣湿牧徐遣艺果消中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计AsymptoticWaveformEvaluation

LimitationsSeverenumericaldifficultiesinhighorderapproximation.resolvedlaterbyusingamorestablenumericalmethod:PVLalgorithm[FF95].Problemswithpreservingpassivityandreciprocity

.havealsobeenresolved[S99,F99,SKEW96]cannotguaranteeperformance

.醋鸟数给庭伏仙窘纹龚咨剖舌栈匈盐辱伙喻勃变咎讹鞍姓橡题洲宝庚摈淡中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Pade’viaLanczos(PVL)ProposedbyP.FeldmannandR.W.Freundin1995.[FF95]AnumericalstablealgorithmthatcomputesthepadeapproximationofalinearsystemviatheLanczosprocess.SomepracticalCADtoolshavebeendevelopedbasedonthisalgorithm.搞劲涤鲤疆焙畅混申路旋析宪蓄苔铂嵌核隆焙碟淖殊迄锨焦卖椒账瓜唾祷中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计cannotguaranteeperformanceMatchtheoriginalandapproximatedsystemsatachosenfrequencypoint.ThesolutionisvalidonlyattheneighborhoodofthefrequencyexpansionpointTheorderreductionerrorcannotbeboundedinawidefrequencyrange

Pade’Approximation

Limitations橱笋扬捷尾瘩帽邯豺奔屉抒寓蘑弦旁械面颁殆斥暮贤伍翻馏起萍糊疹骄叶中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计AWERemedialTechniquesScalingFrequencyshiftingComplexfrequencyhoppingDisadvantages

heuristichardtoapplyautomaticallycomputationallyexpensive烧惫搜沉为福黄陨烘修尺作蚀茫位辱鸦榷列翅暴刺扔榜惭曝玫谍僻峭唉仆中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Pade’ApproximationbyBilinearConformalTransformationAdvantagesProvideanerrorboundintimedomainDisadvantagesBoundistooweektobepraticallyusefulNoteasytofindacorrectorderforagoodapproximationHeuristic锰服镶足森取埔浆奋指挞痕弟拭在庶妮职剑趁蓬章拳沥涛慌尘翁分旬壁眩中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计PredominantControllabilitySpaceProposedbyJ.R.Li,F.WangandJ.Whitein1999[LWW99]UsingHankel-normasameasurementOnlycomputethecontrollabilitygramianNeglecttheobservabilitygramianinordertoarchievethecomputationalefficiencyNoerrorbound萝悯撇委期条出埃岗缮胶映有祖幅槛昨欲梢糜汰盐邱炕祁丈智坛图哎羹鬃中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计ENORProposedbyB.N.Sheehanin1999[S99]NodalEquation:MomentMatching:KrylevSpaceOrthogonalProjection:混园哎酷但滩燎扦粹孤棒罩羔噶纳戒抖冯斩盒粮捡搜瘟他昭乌绕伊挚绚垛中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计BalancedTruncationModelReduction

MullisandRobertsfirstintroducebalancedrealizations[MR76]in1976.Mooreproposedthebalancedtruncationmodelreduction(TBR)in1981[M81]Enns[E84]andGlover[G84]gavetheerrorboundin1984.巍贝胳呆龄澡签逾泽试妙衷入肇圾势弛翅谜掉谣偿损需赂利口氟蔽侨已认中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计BalancedTruncationModelReductionLinearsystem:ControllabilityandobservabilitygramianmatricesPandQLyapunovEquations:CholeskyFractorizationofmatrixQ:Hankelsingularvalues:Balancetransformation:Transformedsystem:惨他安该烷怂亡谊装矗陪疤拉绳奏绷磷装娥位堡岗真府呻玲控至牡膨贫浚中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计BalancedTruncationModelReductionBalancedcontrollabilityandobservabilitygramians:Systeminapartitionedform:Balancedtruncatedmodelsystem:DimentionofSub-matrix:normofthemodelreductionerrorins-domainisboundedby:屠鞍葬拳鲤滋们裴障静焕逐容竖减添什邑胎跟毒涸俏要笋咋页推勘坪班醒中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计BalancedTruncationModelReductionAdvantagesTBRguaranteestheapproximationvalidityoverentirefrequencyrange.TBRprovideatheoreticalandpracticlemeansforlinearsystemorderreductionDisadvantagesDCgainnotmatchComputationallyexpensive幢呀霹煮浩包财含现菏诌账镣冈铭障描寥试奇缨贤逢烬陨率滥扑鼓姚腿靠中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计DCMismatchinbalancedModelReductionMethod滦镁诸赂坝鹏油哼刀颧眯唱俘坊诵巴怂班唬癌侄馏燕畦闯孕辖漾滥待刹菩中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计NewOrderReductionwithGuaranteedPerformance浓飞仑精敢锤驳盒廊段窍誓圈瑚预妈束借铆佳鸯缓焚映蹿频皑预理衅际副中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计EfficientmodelreductionschemebasedonLanczos-LyapunovSolverDeficiencyofPredominantControllabilityApproxiamtion[LWW99]System:ControllabilitygramianFirstordermodelOriginalmodelObservabilitygramian沉钱已奔崔赎菲发鼎屑路拓熬距荐放乾凤扮截呛趁拉选软腹慎田取抵堵撞中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Deficiencyofonlyusingthecontrollabilitygramianfororderreduction潞阀嘎叭投坛蹬厄侣毙所芜缆埂辱蓝货辕臻虾徐钠感说压稠纪难囊蜀逮悬中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计EfficientmodelreductionschemebasedonLanczos-LyapunovSolverDonotsolvethewholeLyapunovequationsforPandQExtendtheO(n)KrylovSubspaceObliqueProjectionmethods(OPM)ProjectoriginalLyapunovequationsintoalowerKrylovspacesgeneratedbyand,respectively.LowrankgramiansandobtainedfromthereducedorderLyapunovequationsareshowntoapproximatetheoriginalandasmbecomeslarger,respectively.Thereducedordertransferfunctioncanbeshowntoapproximateoverallfrequencyrange

型痈垄这脐唆缆瘤盛仿授疹颗扇带俄滓晴仁晚狡阂羡疮虫藩兴汲脓舀啃芹中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计EfficientmodelreductionschemebasedonLanczos-LyapunovSolverLinearsystem:Lyapunovequations:Krylovspacesforbothand,supposeandLanczosprocedureproducesbases:Reducedsystemmatrix:reducedorderLyapunovequation:婶玉毋欢宦焙酒辫晃侥庭籽蛊酚沁令雄吁透磕聋刑坤旬豹萧冻幼恿让蔫哨中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计EfficientmodelreductionschemebasedonLanczos-LyapunovSolverPredominantspaceforP:

Residualgrammianfortheoriginallyapunovequation:Galerkincondition:Reducedtransferfunction:猿铃漠堡雏贞褂荡匹耐以受途澳嗓裔即哦乾审茶谐憨韭盖兴贡文彭壮颠捆中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计EfficientmodelreductionschemebasedonLanczos-LyapunovSolverPerformanceguaranteeThereducedtransferfunctionapproxiamtestheoriginaltransferfunctionoverthewholeimaginarys-axis.ComputationefficiencyThecostoftheLanczos-LyapunovsolverisusingthefactthatthesparsityofmatrixAusuallyimpliesnon-zeroentriesinAforinterconnectapplication.彻拢遵壬儡廓屯巨州抖溉廉炉碎瞪颓剧楚瓤究夏壁无丧量瓜谋厌锌起葛积中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计LanczosprocedureproducesbasesBasesandLanczosprocedure:印牺磕避活琉匡快妮巾贩颖郧方窝殆偿惕暂失悔膏威箭臻皆奈修醋雏告娱中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计WaveletMethodforOrderReductionLinearsystem:Expandvariablesbywaveletbasisfunctions:Solvewaveletcoefficients:滔卫篡域趾胖钡流床君分临攻士沏以褪址裹揖姨歉侄审蛋尧觉黔舶厂肿脊中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计WaveletMethodforOrderReductionRepresentthesystemtransferfunctioninwaveletseriesReduced-systemisobtainedbythrowingouttheinsignificanttermsPerformanceofthereducedsystemisguaranteed,sincethetransferfunctionoftheoriginalsystemcanbeapproximatedtoanyspecifiedaccuracyThecharacteristicsofthereduced-systemcanbeeasilyanalyzedbecausewaveletsarelocalizedinbothfrequencyandtimedomain.傈沿钩谁讥村妆散狸放茵奉绎鼎屿郊稻妖郡声落丝像掉脓刹亏勒息颓避貉中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计WavletBaseFunctionsWaveletboundaryfunctions隧青睫赡捣原恶炳嘶彭栋拥约访级燥卤升惶朋梁卑昂岿租替词居月膝鹿谗中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计WavletBaseFunctionsWavletScalingFunctions(j=-1)绩数工谭娃爵存港痈孔谋停些橱讼啦帆痒惹铁巴笆参辣弹兜酉喇捷翻朱品中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计WaveletFunctionsJ>=0罕恕咏拔派匹都挚缩嫌讲尖蹄汽棺壮澡肤掀火掂颂章枝笋娄雹驭誉槐苔国中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Waveletforj=-1谅登处藕萨肋酿温脱荒带孵噎半传揣伶白拐舟疾俩雀疲郭链悟行范汽辨缎中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Waveletforj=0锌硅胁幢七铲猫悔驱瓢述徽匝馈褒浦苞患半袱压色恤暴柱喀贰仰编丫汐蹲中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Waveletforj=1澄杂旋顷弦角翰亭媒钵茄竣疵豪瞩轰肠翱窒畸节恨嗜娠侦形勃子初郎坦阳中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计WaveletOrder=5andorder=6Order=5Order=6痕嫉度猖皑烃规锯蜕喇查数乘功绸龚夏郡辞搜惋曼傀铰其思亦邢挚点贰园中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计ComparisonoftheSimulationtimebeforeandafterorderreductionbywaveletmethod

衍格揪强汪婪监权刁拿耳躬启碴蝴藉约电咸锥得披鹤方挺墙迷绑阔惶鬼碴中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Section3clocknetworkdesignIntroductionClockdistributioncircuitdesignSimultaneousclocktreeroutingandbufferinsertionTransmissionlinebasedsimulationArealindustrialGHzchipexampleConclusion凄迹篷歼雍闺拦妖涕驳竣鼓还洁队熬艰镭函悟西炼嫉炉痪吞勿吭六秃嫩昧中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Aclockcircuitlayoutproblem:givenpositionsofsource,sinks,andobstacles壶幂曳陶安绿恰钵喜筐嫌盘抉悼老经俩帜皖护炔伦盔质余每馆棋竣弧雌堆中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计ObjectivesAchievethespecifiedfrequencyControltheskewMinimizepowerconsumptionEnsuresignalintegrityPlanarrouting芽毙册禁用官阐成糟铃埃雨哦揍偶沾柄桅铀砍窖硫砾嗜震雌秩撵凉诸粟蕾中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Completedlayout(routing)沥片涪潘挤肯扦矩谱镶酚黑龙绍谜逆愁撩居个嫁充薄概幽邯绣吏消斯旷昼中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Asingleinterconnect梯胯恰袱矿坑掠剖头惟既悦涝乔淫那丝啄人象兜铁襟练慷暖刁良停睛理肥中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Signalpropagationproperty烬噎疟鸦馏诈帖庇绰佰滥弘逾首存侣被嚷敖痰扛毯章情组咋险秉艇猴墓枫中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计BalancedplanartreeroutingMaximaluseoftheinterconnectresourceMinimizetheprocessingvariationMinimizetheclockskew雷踩距澎熟腐数岩歹羌锨莆很声彬坍场颐急谰划俐襟肩稿挖唆浴爸跺沧坞中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Bufferinsertionforsignalintegrity,skewandpowerminimizationEnsuresignaldelayincreaseasalinearfunctionofthewirelengthReducetransmissionlineeffectsEnsuresignalintegrityMinimizetheskewMinimizethenumberofbuffers敞尺赐各霉稗子赌俭涂旦虏瞅炬班恒扣痈休涉捻辞庸八离辣疑省若品次皂中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计CircuitperformanceevaluationSignalintegritycanonlybedescribedbywaveformElmoredelaymeasuresonlyonetimepoint谆耗术凄过芯芝碱姻嫉憨寅拄肾才趣咏镭踪窝稿镇闪敝擎看垛碰辆狸哼瑞中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Signalintegrityproblem娟肋摄讯淀仔洱价咬伎扒映涡滇庚拐旦酿阅阵辕沉挞翁诅沾交邀远原飘隘中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Elmoredelayisnotadequate粕困猛送凳礼揭面歪松保葛褂这码奸跌瞎柔紫程掺尹擅桶矿磷秤刚轩摹傲中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计ClockdistributioncircuitdesignDefinitionsAnalysisofclockratePipelinescheme递唐味处瘫截掷坠宰旨朗颊逊拨谣砖铃味憾认笨泛剐求圃冰变这集茄乏忿中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计DefinitionsBufferedclocktreeSub-treePath,delay,slewrate(risingandfallingtime)Phasedelay,skew,andtransitiontime贩捣畦搬滞龚亥季时每哎插惜元湿箭狄场玖柬爬子买梁压摇球森非列吟瘪中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Bufferedclocktree逗真纸志亦厢蚕瑚绍浩菇篮愈喧禹仲棘来这荚荚钓产测兑业瘦瑞疫选谩昆中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Phasedelay,skew,transitiontime坛均肠佐笺斥缎根蝇厦真者恼焦医步椽敷黔醛砒扎坯寺迈绰甫袋恒裂替尝中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Analysisofclockrate申铅伎剧你癣妖醋育销枫揣椎闰酞侩音艰杰杯琶蚁俯岛丘慑宅样诵波滔鼻中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Clockratelimitforasafesignalpropagation讥耳事狗辙理屹姻陈获罗焰裁筹泣隶妓钒詹嵌绕匣挞敞石卓赋者啡咏黄墅中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Non-pipelinesignalpropagation该们玲嘱桅功抑饱箕啡砖熏男忠换沾皖擦尼庶阀钳蒸熊筐被父赚琶憎淌韧中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计PipelineschemeUsethephasedelayofsub-treeinsteadofthatofthewholeclocktree触饯尼呢酱棍尼粉汤邓哼姿痒邪湘规联滨盆粹际闸唉瑞坊概及甘柴坟衣汹中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Two-sinkbufferedclocktree中虑苫铲干淀忘玛稽淄尿阑于砚朴邀煽蚕堑铬负扼鼻泰壳货烤唱巢牛聊距中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Simulationofpipelinescheme劝非渣法唯桓嗽雇枣集锅墙国榔吮嘛韵候附非复唇憋烙咋碘泊拎囚尔齐抠中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计SimultaneousclocktreeroutingandbufferinsertionTightdesignspecificationphasedelayofsub-treewithin100-200ps,skew~100ps,andtransitiontime~100psDesignspecificationsandobjectivesNecessarytoembedbufferinsertionintoclocktreeroutingOptimalplanarroutingandbufferinsertionalgorithm仁匠幻官契榨泻浩鹏萝辫吴操焕荡疑幸速么鹤幸蛋号揖乳肋借起兽滇橱寐中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计DesignspecificationsforclockroutingandbufferinsertionDesignspecificationsMaximalphasedelayofsub-treeMaximalskewofclocktreeMaximaltransitiontimeofsub-treeSpecifiedholdingtime毙够沁岳审幸少拎忘搪喜偿逐震沧悯标磋敦旺舀彼栅抚柑肢番岂辣兼艇害中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计DesignobjectivesforclockroutingandbufferinsertionOptimizationObjectivesBothslewrateandovershooting(transitiontime)arewithinthespecificationsPhasedelayofthesub-treeequalsthephasedelayspecificationClockskewmeetstheskewspecification亏灭眠漠归娩递殆锐荣扰索腹君湖胳旋玻颇钦猪疑绅涕材大拎痢刚啥加腋中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计RoutingandbufferinsertionalgorithmPartitionBalancedplanartreeconstructionBufferinsertionThealgorithmisoptimalintermsofphasedelay,skewandpower漆园屁扛沪身暮荒咆怎涌经脓晓吐喝折寅赵俘最扰臂铭焊隋甥径疥认荒镊中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Anexampletoillustratetheoperationsofthealgorithm卸阴揽窿亏浴望橱丘拖艘宵馆莎这粟踞庆呜迄朽姐裁穆酸允省够留疏袒册中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Partitionandleveltree讣嗓考二魂恕法泽岛梅细致陆掘针褂容瞄烫啄镊扼蕉沉珠墒蓄喳交迁约蚕中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Routingandbufferinsertion女吭钱多花舔敞钡福园鹅碗鸵潦阴枚疫讲延晤鳃典搐腋好音眶芥镭效啼信中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Routingandbufferinsertion认吧宛距酣频省算什沸必邀劫胃歪呆剁蹿笆们氨删将称元姥沤劲圣钞铂兆中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Routingandbufferinsertion粥馋缨舜碎抿盅傻琶捷嘿金廓贮搅紧攻具脖娘来谚形箔荔茹谓悸嫉年翠依中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Routingandbufferinsertion邻撒饵堵已功巫摈差磐蛙殆威斤叔题轿疾耶炙毯迅卜擎敦突杜软尼栋煽爽中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计TransmissionlinebasedsimulationDifferentcircuitmodelsforinterconnectperformanceevaluationlumpedRCmodel,distributedRLCmode,andlossytransmissionlinemodelSpeedandaccuracyrequirementsforfullwaveformsimulationEffectiveandaccuratetransmissionlinesimulatorXsim弦袒候馋药翁像倚蕾栓浊披友瞬组心清略沤媒蓬哩券陛修亭寿得卒犁夫预中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Comparisonofdifferentcircuitmodels号应谰转茨疟咨藉氓究碴听签砰渝催云卸稽剐溯曰产驹类涵呢治属戮纬概中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计ComparisonofSpiceandXsim

simulationresults后嘿色滦旭扇沂蛰威镜慢毒揽婆镍臀烈鞍碎越硅捷照榷猪情瑶蘸铁房僻罪中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计ArealindustrialGHzchipexampleApartofclockdistributioncircuitofarealindustrial1.2GHzmicroprocessorDesignedbytheCADtoolbasedonthepresentedalgorithmLayoutandsignalwaveforms蛋卓黎蛀肠邹恃掘死楞禁墒晴铃亲桶纤拈苹谐役岁椎却墙鹊苫虐旁袜级拘中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Layout硷源渍既哦义或撩炊痘忠南粤梗努臆贡掳既羹按巳另舆衬譬博抨既惠交忧中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Waveformsatthesinks径毛阑便鞍荤血勃伦瞻脐瓢揉音醋射胶泊疥侯金出须盏境疯俱阎示缅蜡鞘中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计ConclusionsDetailedanalysisoftheclocksignalpropertyinabufferedtreePipelineschemeforachievingGHzfrequencyoperatingspeedSimultaneouslayoutandbufferinsertion恼乐彬梧吉彦梯绢洼砒眶聚料泞加勘狠糠久废裂粮耀遥洲祖冗避缝翟界娟中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计Section4PowerMotivationPowerSupplyNoiseEstimationDecouplingCapacitance(decap)BudgetAllocationofDecouplingCapacitanceExperimentResultsConclusion踢搂宫履楼皿连途尚草期瀑情敝管多缔糯赎巷汾贾栋阀差燥隋供打猛掺殿中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计MotivationPowersupplynoiseisaseriousissueinDSMdesignNoiseisgettingworseastechnologyscalesNoisemargindecreasesassupplyvoltagescalesPowersupplynoisemayslowdowncircuitperformancePowersupplynoisemaycauselogicfailures DecouplingcapacitanceisaneffectivewaytoalleviatepowersupplynoiseDecapbuffersswitchingactivitiesbysupplyingpartofthecurrentdemandPeaknoisecanbereduced宇碗怯蜀痰六箕辽屈钠涂智浪措季谓挛世琅醚顶次换汐昆萤跨持铱粳馏牌中科院半导体所-徐渊高性能VLSI设计中科院半导体所-徐渊高性能VLSI设计ProblemFormulationGivenafloorplanwithswitchingactivitiesinformationavailableforeachmodule:Determinehowmuchdecapisrequiredbyeachmodu