数字集成电路：互连问题

数字集成电路

-电路、系统与设计互连问题互连的寄生效应•降低电路性能•影响信号完整性

增加延时

增加额外功耗寄生效应类型•电容的•电阻的•电感的互连DealingwithCapacitance电容和可靠性-串扰动态电路中的串扰3x1mmoverlap:0.19VdisturbanceCYCXYVDDPDNCLKCLKIn1In2In3YX2.5V0V驱动线的电容耦合tXY=RY(CXY+CY)V(Volt)00.50.450.40.350.30.250.20.150.10.05010.80.6t(nsec)0.40.2XYVXRYCXYCYtr↑克服电容串扰的方法避免浮空节点保持敏感节点尽可能增大上升/下降时间采用差分信号不要使两条信号线之间电容太大采用屏蔽线采用额外布线层屏蔽层GNDGND屏蔽线衬底(GND)屏蔽层VDD电容和CMOS电路性能Cc-

Whenneighboringlinesswitchinoppositedirectionofvictimline,delayincreasesDELAYDEPENDENTUPONACTIVITYINNEIGHBORINGWIRES米勒效应

-Bothterminalsofcapacitorareswitchedinoppositedirections

(0

Vdd,Vdd

0)-Effectivevoltageisdoubledandadditionalchargeisneeded

(fromQ=CV)串扰对延时的影响risratiobetweencapacitancetoGNDandtoneighbor密集型布线结构发射互连

低介电常数BothdelayandpowerarereducedbydroppinginterconnectcapacitanceTypesoflow-kmaterialsinclude:inorganic(SiO2),organic(Polyimides)andaerogels(ultralow-k)Thenumbersbelowareonthe

conservativesideoftheNRTSroadmape编码数据消除最坏情形的翻转能够使总线加速编码器译码器总线InOut驱动大电容VinVoutCLVDD

晶体管尺寸

叠加缓冲器使用叠加缓冲器CL=20pFInOut12N0.25mmprocessCin

=

2.5

fFtp0=30psF=CL/Cin

=8000fopt=3.6N=7tp

=0.76ns(SeeChapter5)输出驱动器设计TradeoffPerformanceforAreaandEnergyGiventpmaxfindNandfAreaEnergy缓冲器级数N10135791110,0001000100tp/tp0F=100F=1000F=10,000tp/tp0输出驱动器设计TransistorSizesforoptimally-sizedcascadedbuffertp

=0.76ns设计考虑--宽晶体管的实现G(栅)S(源)D(漏)多个接触压焊块设计压焊块OutInVDDGND100mmGNDOutESD保护Whenachipisconnectedtoaboard,thereisunknown(potentiallylarge)staticvoltagedifferenceEqualizingpotentialsrequires(large)chargeflowthroughthepadsDiodessinkthischargeintothesubstrate–needguardringstopickitup.ESD保护二极管封装Bondwires(~25m)areused

toconnectthepackagetothechip

Padsarearrangedinaframe

aroundthechipPadsarerelativelylarge

(~100min0.25mtechnology),

withlargepitch(100m)Manychipsareasare‘padlimited’框架版图实际照片封装Analternativeis‘flip-chip’:PadsaredistributedaroundthechipThesolderingballsareplacedonpadsThechipis‘flipped’ontothepackageCanhavemanymorepads三态缓冲器InEnEnVDDOutOut=In.En+Z.EnVDDInEnEnOut增加输出驱动减小摆动

Reducingtheswingpotentiallyyieldslinear

reductionindelayAlsoresultsinreductioninpowerdissipationDelaypenaltyispaidbythereceiverRequiresuseof“senseamplifier”torestoresignallevelFrequentlydesigneddifferentially(e.g.LVDS)单点静态驱动器和接收器CLVDDVDDVDD驱动器接收器VDDLVDDLInOutOut动态降低摆幅电路互连DealingwithResistance电阻的影响WehavealreadylearnedhowtodriveRCinterconnectImpactofresistanceiscommonlyseeninpowersupplydistribution:IRdropVoltagevariationsPowersupplyisdistributedtominimizetheIRdropandthechangeincurrentduetoswitchingofgates噪声容限M1XIR9RDVfpreDVVDDVDD2DV9I电阻和功耗

分类问题Source:Cadence

RequiresfastandaccuratepeakcurrentpredictionHeavilyinfluencedbypackagingtechnologyBeforeAfter能量分配Low-leveldistributionisinMetal1Powerhastobe‘strapped’inhigherlayersofmetal.ThespacingissetbyIRdrop,electromigration,inductiveeffectsAlwaysusemultiplecontactsonstraps功耗3层金属(EV4)3rd“coarseandthick”metallayeraddedtothetechnologyforEV4designPowersuppliedfromtwosidesofthedievia3rdmetallayer2ndmetallayerusedtoformpowergrid90%of3rdmetallayerusedforpower/clockroutingMetal3Metal2Metal1CourtesyCompaq4层金属(EV5)4th“coarseandthick”metallayeraddedtothetechnologyforEV5designPowersuppliedfromfoursidesofthedieGridstrappingdoneallincoarsemetal90%of3rdand4thmetalsusedforpower/clockroutingMetal3Metal2Metal1Metal4CourtesyCompaq2referenceplanemetallayersaddedtothetechnologyforEV6designSolidplanesdedicatedtoVdd/VssSignificantlylowersresistanceofgridLowerson-chipinductance6层金属–EV6Metal4Metal2Metal1RP2/VddRP1/VssMetal3CourtesyCompaq电迁移(1)电迁移(2)电阻率和性能Diffusedsignal

propagationDelay~L2CN-1CNC2R1R2C1TrVinRN-1RNThedistributedrc-line总线问题ChallengesNofurtherimprovementstobeexpectedaftertheintroductionofCopper(superconducting,optical?)DesignsolutionsUseoffatwiresInsertrepeaters—butmightbecomeprohibitive(power,area)EfficientchipfloorplanningTowards“communication-based”designHowtodealwithlatency?Issynchronicityanabsolutenecessity?()outwwdoutdwwdCRCRCRCRT+++=693.0377.0发射互连:铜Copperisplannedinfullsub-0.25mmprocessflowsandlarge-scaledesigns(IBM,Motorola,IEDM97)Withcladdingandothereffects,Cu~2.2mW-cmvs.3.5forAl(Cu)

40%reductioninresistanceElectromigrationimprovement;100Xlongerlifetime(IBM,IEDM97)Electromigrationisalimitingfactorbeyond0.18mmifAlisused(HP,IEDM95)Vias互连:

各层配线#ofmetallayersissteadilyincreasingdueto:

Increasingdiesizeanddevicecount:weneedmorewiresandlongerwirestoconnecteverything

Risingneedforahierarchicalwiringnetwork;localwireswithhighdensityandglobalwireswithlowRC0.25mmwiringstack曼哈顿布线与对角线布线yxdestinationManhattansourcediagonal

20+%InterconnectlengthreductionClockspeed

Signalintegrity

Powerintegrity

15+%Smallerchips

plus30+%viareductionCourtesyCadenceX-initiative使用旁路驱动器多晶硅字线多晶硅字线金属字线金属旁路从二端驱动字线采用金属旁路字线字线K个单元减小RC延时Repeater(chapter5)中继器(再次考虑)TakingtherepeaterloadingintoaccountForagiventechnologyandagiveninterconnectlayer,thereexistsanoptimallengthofthewiresegmentsbetweenrepeaters.Thedelayofthesewiresegmentsisindependentoftheroutinglayer!互连DealingwithInductanceLdi/dtImpactofinductanceonsupplyvoltages:ChangeincurrentinducesachangeinvoltageLongersupplylineshavelargerLCLV’DDVDDLi(t)VoutVinGND’LLdi/dt:模拟Ldi/dt解决办法SeparatepowerpinsforI/Opadsandchipcore.Multiplepowerandgroundpins.Carefulselectionofthepositionsofthepowerandgroundpinsonthepackage.Increasetheriseandfalltimesoftheoff-chipsignalstothemaximumextentallowable.Schedulecurrent-consumingtransitions.Useadvancedpackagingtechnologies.Adddecouplingcapacitancesontheboard.Adddecouplingcapacitancesonthechip.选择正确引线去耦电容片上去耦电容EV4totaleffectiveswitchingcapacitance=12.5nF 128nFofde-couplingcapacitancede-coupling/switchingcapacitance~10xEV513.9nFofswitchingcapacitance160nFofde-couplingcapacitanceEV634nFofeffectiveswitchingcapacitance320nFofde-couplingcapacitance--notenough!Source:B.Herrick(Compaq)EV6片上去耦电容Designfor

Idd=25A@Vdd=2.2V,f=600MHz0.32-µFofon-chipde-couplingcapacitancewasaddedUndermajorbussesandaroundmajorgriddedclockdriversOccupies15-20%ofdiearea1-µF2-cm2

WirebondAttachedChipCapacitor(WACC)significantlyincreases“Near-Chip”de-coupling160Vdd/Vss

bondwirepairsontheWACCminimizeinductanceSource:B.Herrick(Compaq)EV6WACCSource:B.Herrick(Compaq)传输线波长等式VinVoutrgcrrxgcrgcgcllll设计规则Transmissionlineeffectsshouldbeconsideredwhentheriseorfalltimeoftheinputsignal(tr,tf)issmallerthanthetime-of-flightofthetransmissionline(tflight).tr(tf)<<2.5tflightTransmissionlineeffectsshouldonlybeconsideredwhenthetotalresistanceofthewireislimited:

R<5Z0Thetransmissionlineisconsideredlosslesswhenthetotalresistanceissubstantiallysmallerthanthe