EDA技术与应用讲义-第9章第2节-Quartus-II中的设计优化

第9章第2节

QuartusII中的优化设计

配置、仿真和报告

<EDA技术与应用>课程讲义下一章上一章南海学院刘刚本节内容时序分析的根本概念和术语QuartusII中的时序约束设置QuartusII中的时序分析QuartusII中的编译报告FPGA芯片的时序指标举例有关时序分析更多的资料请参见时序分析的根本概念和术语时钟建立时间(tSU:clocksetuptime)时钟保持时间(th:clockholdtime)时钟输出延时(tCO:Clocktooutputdelay)时钟偏斜〔ClockSkew〕引脚到引脚的延时(tPD:Pin-to-PinDelay)时序裕量〔Slack〕独立时钟和衍生时钟〔AbsoluteClock&DerivedClock〕占空比〔DutyCycle〕行波时钟〔RippleClock〕建立时间和保持时间tSU=DataDelay+MicrotSU-ClockDelaytSU(clocksetuptime)tH=ClockDelay+MicrotH-DataDelaytH(clockholdtime)tCO(Clocktooutputdelay)tCO=ClockDelay+MicroTco+DataDelay时钟偏斜〔clockskew〕:图示时钟偏斜〔clockskew〕Thedifferenceinthearrivaltimeofaclocksignalattwodifferentregisters,whichcanbecausedbypathlengthdifferencesbetweentwoclockpaths,orbyusinggatedorrippledclocks.Clockskewisthemostcommoncauseofinternalholdviolations,asshowninfigure1引脚间延时tPD(pin-to-pindelay)

Thetimerequiredforasignalfromaninputpintopropagatethroughcombinationallogicandappearatanexternaloutputpin.IntheQuartus®

IIsoftware,youcanspecifytherequiredtPDfortheentireprojectand/orforanyinputpin,outputpin,bidirectionalpin.

Youcanalsoassignapoint-to-pointtPDassignmenttospecifytherequireddelaybetweenaninputpinandaregister,aregisterandaregister,aregisterandanoutputpin.时序裕量〔Slack〕Slackisthemarginbywhichatimingrequirementwasmetornotmet.Apositiveslackvalue,displayedinblack,indicatesthemarginbywhicharequirementwasmet.Anegativeslackvalue,displayedinred,indicatesthemarginbywhicharequirementwasnotmet.Slacktimeiscalculatedusingthefollowingequation:

slack=<requiredmaximumP2Ptime>-<actualmaximumP2Ptime>TimingAnalyzerSummaryTypeSlackRequiredTimeActualTimeWorst-casetsuN/ANone4.500nsWorst-casetcoN/ANone10.900nsWorst-casethN/ANone1.000nsWorst-caseMinimumtcoN/ANone9.600nsClockSetup:'clk'N/ANone96.15MHz独立时钟和衍生时钟

〔absoluteclock&derivedclock〕概念：absoluteclock

不依赖于其他时钟信号而存在的时钟derivedclock

由某个absoluteclock

经过相移、分频、倍频而得到的时钟时序分析的处理：一个设计可以允许有多个独立时钟存在只对一个独立时钟内相关的所有信号进行时序分析占空比〔Dutycycle(%)〕Indicatesthepercentageoftimethatthesignalishighorlowduringthetimeperiod.行波时钟〔RippleClock〕不建议使用D触发器输出作为驱动时钟QuartusII中的时序约束设置：目的目的：时序约束对设计的编译过程起着重要作用布局布线工具将对最差的时序路径进行最多的努力对于不满足时序设置的路径将以“红色”显示出来QuartusII中的时序约束设置：内容可以进行那些时序约束设置？内部

时序约束设置I/O

时序约束设置最大

时序约束设置最小

时序约束设置全局 时序约束设置单个节点或模块 时序约束设置QuartusII中的时序约束设置：步骤先进行全局设置，再进行单个设置单个设置的优先级别高于全局设置〔在2者冲突的情况下〕方法：通过菜单窗口设置:Assignments->TimeSetingsAssignments->Setings->TimingRequire&Options通过修改“.QSF”文件设置全局时序设置建立延时输出延时引脚间延时时钟频率最小输出延时最小保持延时最小引脚间延时剪除选项CutOptionsCutOffFeedbackfromI/OPinsCutOffClearandPresetSignalPathsCutOffReadDuringWriteSignalPathsCutPathsbetweenUnrelatedClockDomains单个时钟设置〔InvididualClock〕独立时钟设置衍生时钟设置QuartusII中的时序分析报告类型

文件扩展名Analysis&Synthesis分析与综合.map.rptAssembler.asm.rptCompilation（Thisreportfileisasinglefilethatcombinestheinformationoftheindividualmodulecompilationreportfiles.）编译.cmp.rptDesignAssistant.drc.rptEDANetlistWriter.eda.rptFitter.fit.rptFlow.flow.rptSimulator.sim.rptTimingAnalyzer.tan.rptQuartusII中的编译报告文件FPGA芯片的时序指标Theend

Theend.

以下内容

为

正文的引用，

可不阅读。建立时间和保持时间返回CutOffClearandPresetSignalPaths

Cutsoffthetimingpathsforallclearandpresetsignalsinthecurrentdesign.Whenyouturnthisoptionon,theTimingAnalyzerdoesnotconsiderthedelayalongthesepathsduringtiminganalysis.WhenyouturnCutoffclearandpresetsignalpathson,theTimingAnalyzerdoesnotincludeclearandpresetsignalstoaDflipflopinthetiminganalysis.Cuttingoffthesepathsmayhelpeliminateinvalidpathsfromthetiminganalysis.返回CutOffFeedbackfromI/OPins

Cutsoffthedelaythatisfedbackfromabidirectionalpinduringtiminganalysis.Youcanuseabidirectionalpinasbothaninputpinandoutputpin.Whenyouturnon

CutofffeedbackfromI/Opins,thetiminganalysisdoesnotincludesignalfeedbackfromwithinthedevice,thuseliminatinginvalidpaths.CutofffeedbackfromI/Opinsisespeciallyusefulwhenyouconnectabidirectionalpindirectlyorindirectlytoboththeinputandtheoutputofalatch.Thistypeoffeedbackpathiscontinuousbecauseclockedlogicprimitivescannotinterruptthepath.AstheTimingAnalyzerencountersadditional,interconnectedlatch-to-pinloops,thenumberofhiddenpathsgrowsexponentially,forexample,whenyouuselatcheswithbidirectionalbuses.CutofffeedbackfromI/Opinsallowsyoutoeasilyeliminatethefalsepathscausedbylatch-to-pinloops.返回CutOffReadDuringWriteSignalPaths

CutsoffthedelayfromthewriteenableregisterthroughtheEmbeddedSystemBlock(ESB)toanydestinationregisterduringtiminganalysis.WhenyouturnCutoffreadduringwritesignalpathson,theTimingAnalyzerdoesnotconsiderthedelayalongthesepathsduringtiminganalysis.IfyourdesignreadsthedatafromtheESBasitiswritten,youmaywanttoturnoffCutoffreadduringwritesignalpaths.However,ifyourdesigndoesnotreadthedatafromtheESBasitiswritten,thedelayfromthesepathscancausemisleadingresultsinyourtiminganalysisunlessyouturnonCutoffreadduringwritesignalpaths.返回CutPathsbetweenUnrelatedClockDomainsEliminatesthepathsbetweenunrelatedclockdomainsfromthetiminganalysis.WhenyouturnCutpathsbetweenunrelatedclockdomainson,theTimingAnalyzerignoresthedelayalongthesepathsduringtiminganalysis.返回UsingI/OTimingRequirements

TheQuartusIITimingAnalyzerprovidestwomethodsforspecifyingI/Otimingrequirements.YoucanspecifyI/OtimingrequirementsusingthetraditionaltsuRequirement,tcoRequirement,and/orthRequirementtimingassignments(resultsreportedinthetsu,th,andtcoTimingAnalyzerreports),oryoucanincludethesepathsaspartoftheclockanalysisbyusingtheInputMaximumDelay,InputMinimumDelay,OutputMaximumDelay,orOutputMinimumDelayassignmentstospecifydelaysbasedonexternaldevicetiming(resultsreportedinClockSetuporClockHoldTimingAnalyzerreports).BothtypesofI/Otimingrequirementsultimatelyproducesimilarresultsthroughdifferentmethods.ThefollowingexampleillustratesthissimilaritybyshowinghowassigningeitheratsuRequirementorInputMaximumDelayrequirementachievesarequiredclockperiod.Theexampleassumesa10nsclockperiodrequirement,4nsexternaldelay,andzeroclockdelay(forsimplification).参见图示twomethodsfor

specifyingI/Otimingrequirements.TwoorMoreRegisterOutputsinCascadeShouldNotDirectlyDriveClockPortsofFollowingRegisters(DesignAssistantRule)

Adesignshouldnotcontainrippleclockstructures,thatis,structureswheretheoutputsoftwoormoreregistersinacascadeeachdirectlydrivestheinputclockportofthefollowingregisterinthecascade.ThefollowingimageshowsanexampleofarippleclockstructureEachstageofarippleclockstructurecausesphasedelay,whichaccumulatesandresultsinlargeskewsinthestructure'soutputsignal;thelargeskewcancauseproblemswhenyouusetherippleclockstructureasaclocksignalforothercircuits.Eachstageofarippleclockstructurealsocausesanewclockdomaintobedefined;theadditionalclockdomainsmaketiminganalysisofthedesignmorecomplexandtime-consuming.Rippleclockstructuresareoftenusedtomakecountersoutofthesmallestamountoflogicpossible.However,inallAltera®devicessupportedbytheQuartus®

IIsoftware,usingarippleclockstructuretoreducetheamountoflogicusedforacounterisunnecessarybecausethedeviceallowsyoutoconstructacounterusingonelogicelementpercounterbit.返回tSU(clocksetuptime)

Thelengthoftimeforwhichdatathatfeedsaregisterviaitsdataorenableinput(s)mustbepresentataninputpinbeforetheclocksignalthatclockstheregisterisassertedattheclockpin.IntheQuartus®

IIsoftware,youcanspecifyarequiredtSUfortheentireprojectand/orforanyinputpin,bidirectionalpin,inputregister,orclock.Youcanalsospecifyapoint-to-pointtSUrequirementbetweenaninputpinandaregister.TheTimingAnalyzercalculatestSUusingthefollowingequation: tSU=<pintoregisterdelay> +<microsetupdelay>-<clocktodestinationregisterdelay>返回tH(clockholdtime)

Theminimumlengthoftimeforwhichdatathatfeedsaregisterviaitsdataorenableinput(s)mustberetainedataninputpinaftertheclocksignalthatclockstheregisterisassertedattheclockpin.IntheQuartus®

IIsoftware,youcanspecifyarequiredtHfortheentireprojectand/orforanyinputpin,bidirectionalpin,inputregister,orclock.Youcanalsospecifyapoint-to-pointtHrequirementbetweenaninputpinandaregister.TheTimingAnalyzercalculatestHusingthefollowingequation:tH=<clocktodestinationregisterdelay>+<microholddelayofdestinationregister>-<pintoregisterdelay>返回tCO(Clocktooutputdelay)

Themaximumtimerequiredtoobtainavalidoutputatanoutputpinthatisfedbyaregisterafteraclocksignaltransitiononaninputpinthatclockstheregister.Thistimealwaysrepresentsanexternalpin-to-pindelay.IntheQuartus®

IIsoftware,youcanspecifytherequiredtCOfortheentireprojectand/oranyclocksignal,anyregisterdrivinganoutputorbidirectionalpin,oranyoutputorbidirectionalpindrivenbyaregister.Youcanalsospecifyapoint-to-pointtCOrequirementbetweenaclockandaregister,aclockandanoutputpin,oraregisterandanoutputpin.tCOiscalculatedusingthefollowingequation:tCO=<clocktosourceregisterdelay> +<microclocktooutputdelay> +<registertopindelay>返回DesignAssistantRulesClock

CombinationallogicusedasclocksignalshouldbeimplementedaccordingtoAltera®standardscheme

Invertershouldnotbeimplementedinlogiccell

Inputclockpinshouldfanouttoonlyonesetofcombinationallogicusedasclocksignal

Clocksignalsourceshoulddriveonlyinputclockports

Clocksignalshouldbeaglobalsignal

Clocksignalsourceshouldnotdriveregistersthataretriggeredbydifferentclockedges

Reset

Combinationallogicusedasresetsignalshouldbesynchronized

Externalresetshouldbesynchronizedusingtwocascadedregisters

Externalresetshouldbecorrectlysynchronized

Resetsignalsourceshoulddriveonlyinputresetports

Resetsignalthatisgeneratedinoneclockdomainandusedinother,asynchronousclockdomainsshouldbesynchronized

Resetsignalthatisgeneratedinoneclockdomainandusedinother,asynchronousclockdomainsshouldbecorrectlysynchronized

TimingClosure

Nodeswithmorethanspecifiednumberoffan-outs:<n>

Topnodeswithhighestfan-out:<n>

Registeroutputdirectlydrivesinputofanotherregisterwhenbothregistersaretriggeredatsametime

Registersindirectdatatransferbetweenclockdomainsaretriggeredbyclockedgesatthesametime

Non-synchronousdesignstructure

Designshouldnotcontaincombinationalloops

Registeroutputshouldnotdriveitsowncontrolsignaldirectlyorthroughcombinationallogic

Designshouldnotcontaindelaychains

Twoormoreregisteroutputsincascadeshouldnotdirectlydriveclockportsoffollowingregisters

PulsesshouldbeimplementedaccordingtoAlterastandardscheme

Multiplepulsesshouldnotbegeneratedindesign

DesignshouldnotcontainSRlatches

Designshouldnotcontainlatches

CombinationallogicshouldnotdirectlydrivewriteenablesignalofasynchronousRAM

Designshouldnotcontainasynchronousmemory

Signalrace

Outputenableandinputoftri-statenodeshouldnotbedrivenbysamesignalsource

Asynchronousclockdomains

Databitsarenotsynchronizedwhentransferredbetweenasynchronousclockdomains

Alldatabitsthataretransferredbetweenasynchronousclockdomainsaresynchronized

Databitsarenotcorrectlysynchronizedwhentransferredbetweenasynchronousclockdomains

HardCopy™rules

OnlyoneVREFpinshouldbeassignedtoHardCopytestpininanI/Obank

PLLdrivesmultipleclocknetworktypes

Assignmentchecking

Designismissingfmaxrequirement

Designismissingtco,tpd,ortsurequirement

保持时间关系：图

1保持时间关系：图2保持时间关系：图2holdrelationship〔1〕Theassumedholdtimingrelationshipbetweenthesourceanddestinationclocksinamulticyclepath.TheTimingAnalyzerassumesthemoststringentholdrelationship(0nsbydefault)whenanalyzingpathsbetweenregisters.TheTimingAnalyzerperformsthefollowingtwoholdcheckstoverifythateachdesignmeetstheconditionsofthedefaultholdrelationship.TheTimingAnalyzerreportsaninternalholdviolationintheClockHoldsectionoftheCompilationReportwhenareceivingclockispresentedwithdatathatdoesnotmeettheseholdrelationshipchecks.

Guidelinesholdrelationship〔2〕Holdrelationshipcheck1Verifiesthatdatafromthesourceclockedge,whichfollowsthesetuplaunchedge,isnotlatchedbythesetuplatchedge.Holdrelationshipcheck2Verifiesthatdatafromthesetuplaunchedgeisnotlatchedbythedestinationclockedgethatprecedesthesetuplatchedge.Thefollowingillustrationshowsthedefaultholdrelationshipforamultifrequencypath.holdrelationship〔3〕YoucanrelaxthedefaultholdrelationshipinvariouswaysbyassigningtheHoldRelationship,MinimumDelay,MulticycleHold,SourceMulticycleHold,ClockEnableMulticycleHold,orClockEnableSourceMulticycleHoldtimingassignments.Figure2showshowassigningaMulticycleHoldvalueof2affectstheholdrelationship.Bydefault,theTimingAnalyzerassumesthattheDefaultMulticycleHoldsettingisthesameastheMulticyclesetting.Therefore,ifyouassignaMulticycle,SourceMulticycle,ClockEnableMulticycle,orClockEnableSourceMulticycleassignment,thecorrespondingholdrequirementissimilarlychangedunlessyouspecifyaspecificvaluefortheholdrequirement.Forexample,figure3showshowtheholdrequirementisaffectedbybothanimpliedandspecifiedholdrequirement.内部保持时间违规：图1内部保持时间违规：图2CauseofInternalHoldViolationsAninternalholdviolationoccurswhenareceivingclockispresentedwithdatathathasnotmettheholdrequirement.Thisconditionusuallyoccursbecauseofclockskewintroducedbygatedclocksinthedesign.Theexamp