锁相环原理及应用

锁相环原理及其应用ＡＦＣ电路是以消除频率误差为目的的反馈控制电路。由于它的基本原理是利用频率误差电压去消除频率误差,所以当电路达到平衡状态之后,必然有剩余频率误差存在,即频差不可能为零。这是一个不可克服的缺点。锁相环路也是一种以消除频率误差为目的的反馈控制电路。但它的基本原理是利用相位误差电压去消除频率误差,所以当电路达到平衡状态之后,虽然有剩余相位误差存在,但频率误差可以降低到零,从而实现无频差的频率跟踪和相位跟踪。而且,锁相环还具有可以不用电感线圈、易于集成化、性能优越等许多优点,因此广泛应用于通信、雷达、制导、导航、仪表和电机等方面。工作原理锁相环是一个相位负反馈控制系统。它由鉴相器(PhaseDetector,缩写为PD)、环路滤波器(LoopFilter,缩写为LF)和电压控制振荡器(VoltageControlledOscillator,缩写为VCO)三个基本部件组成,如图所示。图锁相环的基本构成设参考信号为(8―10)若参考信号是未调载波时,则θr(t)=θr=常数。设输出信号为(8―11)两信号之间的瞬时相差为（8―12）由频率和相位之间的关系可得两信号之间的瞬时频差为(8―13)

锁定后两信号之间的相位差表现为一固定的稳态值。即（8―14）此时,输出信号的频率已偏离了原来的自由振荡频率ω0(控制电压uc(t)=0时的频率),其偏移量由式(8―13)和(8―14)得到为

(8―15)这时输出信号的工作频率已变为(8―16)图4046方框图AbsoluteMaximumRatings(Note1)(Note2)RecommendedOperatingConditions(Note2)Note1:“AbsoluteMaximumRatings”arethosevaluesbeyondwhichthesafetyofthedevicecannotbeguaranteed.Theyarenotmeanttoimplythatthedevicesshouldbeoperatedattheselimits.Thetableof“RecommendedOperatingConditions”and“ElectricalCharacteristics”providesconditionsforactualdeviceoperation.Note2:VSS=0Vunlessotherwisespecified.DCElectricalCharacteristics(Note2)Note3:Capacitanceisguaranteedbyperiodictesting.Note4:IOHandIOLaretestedoneoutputatatime.DCSupplyVoltage(VDD)-0.5to+18VDCInputVoltage(VIN)-0.5toVDD+0.5VDCStorageTemperatureRange(TS)-65°Cto+150°CPowerDissipation(PD)Dual-In-Line700mWSmallOutline500mWLeadTemperature(TL)(Soldering,10seconds)260°CDCSupplyVoltage(VDD)3to15VDCInputVoltage(VIN)0toVDDVDCOperatingTemperatureRange(TA)-40°Cto+85°CSymbolParameterConditions-40°C+25°C+85°CUnitsMinMaxMinTypMaxMinMaxIDDQuiescentDeviceCurrentPin5=VDD,Pin14=VDD,Pin3,9=VSSVDD=5V200.00520150mAVDD=10V400.0140300mAVDD=15V800.01580600mAPin5=VDD,Pin14=Open,Pin3,9=VSSVDD=5V70555205mAVDD=10V53020410710mAVDD=15V15005012001800mAVOLLOWLevelOutputVoltageVDD=5V0.0500.050.05VVDD=10V0.0500.050.05VVDD=15V0.0500.050.05VVOHHIGHLevelOutputVoltageVDD=5V4.954.9554.95VVDD=10V9.959.95109.95VVDD=15V14.9514.951514.95VVILLOWLevelInputVoltageVDD=5V,VO=0.5Vor4.5V1.52.251.51.5VComparatorandSignalInVDD=10V,VO=1Vor9V3.04.53.03.0VVDD=15V,VO=1.5Vor13.5V4.06.254.04.0VVIHHIGHLevelInputVoltageVDD=5V,VO=0.5Vor4.5V3.53.52.753.5VComparatorandSignalInVDD=10V,VO=1Vor9V7.07.05.57.0VVDD=15V,VO=1.5Vor13.5V11.011.08.2511.0VIOLLOWLevelOutputCurrentVDD=5V,VO=0.4V0.520.440.880.36mA(Note4)VDD=10V,VO=0.5V1.31.12.250.9mAVDD=15V,VO=1.5V3.63.08.82.4mAIOHHIGHLevelOutputCurrentVDD=5V,VO=4.6V-0.52-0.44-0.88-0.36mA(Note4)VDD=10V,VO=9.5V-1.3-1.1-2.25-0.9mAVDD=15V,VO=13.5V-3.6-3.0-8.8-2.4mAIINInputCurrentAllInputsExceptSignalInputVDD=15V,VIN=0V-0.3-10-5-0.3-1.0mAVDD=15V,VIN=15V0.310-50.31.0mACINInputCapacitanceAnyInput(Note3)7.5pFPTTotalPowerDissipationfo=10kHz,R1=1MW,R2=¥,VCOIN=VDD/2VDD=5V0.07mWVDD=10V0.6mWVDD=15V2.4图异或门鉴相器(a)原理图；(b)波形；(c)真值表TypicalWaveformEmployingPhaseComparatorIinLockedCondition图异或门鉴相器鉴相特性图边沿触发型（上升沿）数字比相器TypicalWaveformEmployingPhaseComparatorIIinLockedCondition图CMOS数字门电路型压控振荡器原理图可得振荡频率为由于IO受控于uc，故f亦随uc变化，起到了压控振荡器的作用。CMOS数字集成锁相环5G4046(J691、CD4046)中的VCO就是采用这种电路，实际线路如图5-29所示。(5-29)图5-295G4046（J691、CD4046）中的VCO实际线路当N1栅极加上控制电压uc后，它能改变流过P1，亦即流过P2中的电流，起到uc控制充电电流的作用。分析可得式中UTN和UTP分别为N沟道和P沟道场效应管的阈电压。将(5-30)式代入(5-29)式，得到(5-30)(5-31)DesignInformationThisinformationisaguideforapproximatingthevalueofexternalcomponentsfortheCD4046Binaphase-lockedloopsystem.Theselectedexternalcomponentsmustbewithinthefollowingranges:R1,R2≧10k

,RS≧10k

,C1≧50pF.Inadditiontothegivendesigninformation,refertoFigure5,Figure6,Figure7forR1,R2andC1componentselectionsUsingPhaseComparatorIVCOWithoutOffsetVCOWit