通信与电子设计实验硬件连接关系

33脉冲触发开关(4位64M0/1控制开关(8位4个Xilinx Xilinx视频扩展分AlteraCPLDNorFLASH外扩单片扩展子U50：CPLD型号：XC95144XL-10TQ144：familyXC95144XLDeviceXC95144XLSpeed-10Package U46：FPGA型号：XC2V2000：familyVirtex2,deviceXC2V2000。Speed-4。Package U1：ARM型号：三星S3C2410,最高工作时钟200MHzU30：ALTERACPLD型号：EPM7032TC44-10U42：ALTERACPLD型号：EPM7032TC44-10U33：ALTERACPLD型号：EPM7032TC44-10 CPLD1234567899567234输出数码管（动态扫描模式:共阴极a8个数码管的共用正极控bcdefg8个数码管的共阴极控制0/1控制开关（ON接到地，OFF接到KEY1KEY3无无KEY2KEY4无无 FPGA控制所有CPLD12345678938个DIP开关的通断状态通过FPGA_DipSwitch_en和FPGA_DipSwitch_n[3..0]输入到FPGA，其中FPGA_DipSwitch_en为串行数据传递使能信号，当其为高电平(或上升沿)时，FPGA_DipSwitch_n[3..0]数据有效。000~111的状态，0表示ON，1表示OFF。4，32LEDFPGAFPGA_LED_dFPGA_LED_bits[4..0]完成。00000~1，FPGA_LED_d（高电平）还是灭（低电平FPGA_Seg7_HEX[3..0]FPGA_Seg7_en_n用来指示数据传递，即当其为低电平时，FPGA_Seg7_bits[2..0]三、FPGAXC2V2000FPGAS11开关控制四个全局时钟引脚的时钟连（OFF/ONOFFON时提供48MHz的时钟。FPGA式000主串（与模式引脚一起认IO111配置期间是否上011主接高电平时,110从IO101时，相应的控制为高电平;ON时相应的控制为低电平。U55 V2000TDOV8000V2000_TDIU55V2000V8000U47U55V2000没焊时 123456789DS38a8个bcdefgAD/AD板接信名123456789地地地地地地地ADJADJ 方向ED[0-31]16245U42CPLDDC_EMIFA_OE# U35 UARTU41UARTU41 23568’TCE1=’0’TCE2=’0’TCE3=’0’时为’0’,TCE1=’0’DC_AOE=’0’且 DSPU40SST39VF040- NorU42U41 U42U42AJ109BU34,U35 A[0..11]LEDLEDLED PCIPCI无启动模式（默认PCIPROM无效（默认PCIROMBITEMIF8NoNoNoCPU时钟NoCPU时钟0040015021106131184、DSPCLKIN11101201600十、DSPARMHD00~HD15DSP端HPI控制引脚的译码是通过U33EPM7032CPLD实现的，如上图所示。U33将来自ARM的片选信号nGCS3,nGCS5ADDR[0..4]（Laddr[0..4]162245缓冲器）DSPHPI相应的控制信号。控制逻辑(VHDL代码)如下：HCNTRL0<=ADDR1whennGCS3='0'else whennGCS3='1'; whennGCS3='1'; whennGCS3='0'else whennGCS3='1'; whennGCS3='0'else whennGCS3='1'; <=(nWEandnOE)whennGCS3='0'else whennGCS3='1';HDS2 十一、ARMLCD显示模块用的是SHARPLQ035Q7DH01TFT触摸屏模块，其引脚定义见下表，其它内容请参考Cpld-Cpld-Cpld-Cpld-Cpld-Cpld-Cpld-Cpld-5、USB6、8、ARMLIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_unsigned.all; Vcom Samplingstart framesynLCD_LP linesyn ClocksignalofGate DataENDARCHITECTUREBehaviorOFLCD_CONSIGNAL SIGNALcounter_for_mod SIGNALcounter_for_point:std_logic_vector(8downto0); SIGNALs_lcd_cls SIGNALcounter_for_line: SIGNALline_den Interal_dclk<=notLCD_DCLK <=not CASEcounter_for_modWHEN =>WHENOTHERS=>counter_for_mod<=counter_for_mod+"001";ENDEND (VLINE='1')elsif(Interal_dclk'EVENTANDInteral_dclk='0')thenend (counter_for_point="000000110"andline_den='1')then

end

if(Interal_dclk'eventandInteral_dclk='1')thenif(counter_for_point="011111111")thens_lcd_rev<=notendif;endendif(VFRAM='1')thenelsif(s_lcd_cls'eventands_lcd_cls='0')endif;if(counter_for_line>="000000110"andcounter_for_line<="101000101")thenendif;endprocess;if(line_den='1')thenendif; <=nGCS0ANDnGCS1ANDnGCS2ANDnGCS3ANDnGCS4ANDnGCS5ANDnFWEANDtem_buffe