超低功耗iCE40 HX系列架构图分析

超低功耗iCE40HX系列架构图分析lattice公司的iCE40HX超低功耗mobileFPGA系列，和其它任何的CPLD或FPGA器件相比，可提供最低的静态和动态功耗，大约640到7680个逻辑单元和触发器，每个器件包含8到32个RAM区块，每个区块有4Kb存储，用于数据存储和缓冲，特别适合对成本敏感和量大的应用。本文介绍了iCE40HX系列主要特性，iCE40HX系列架构图，主要产品和特性，以及iCEblink40iCE40HX1K评估板主要特性，电路图，主要元件清单和PCB元件布局图。TheLatticeSemiconductoriCE40LP-SeriesandHX-SeriesprogrammablelogicfamilyaredesignedtodelivertheloweststaticanddynamicpowerconsumptionofanycomparableCPLDorFPGAdevice.iCE40FPGAsaredesignedspecificallyforcost-sensitive，high-volumeapplications.iCE40FPGAarefullyuser-programmableandcanself-configurefromaconfigurationimagestoredinon-chip，nonvolatileconfigurationmemory（NVCM）orstoredinanexternalcommoditySPIserialFlashPROMordownloadedfromanexternalprocessoroveranSPI-likeserialport.iCE40componentsdeliverfromapproximately640to7，680logiccellsandflip-flopswhileconsumingafractionofthepowerofcomparableprogrammablelogicdevices.EachiCE40deviceincludes8to32RAMblocks，eachwith4Kbitsstorage，foron-chipdatastorageanddatabuffering.EachiCE40deviceconsistsoffiveprimaryarchitecturalelements.AnarrayofProgrammableLogicBlocks（PLBs）

EachPLBcontainseightLogicCells（LCs）;eachLogicCellconsistsof…Afast，four-inputlook-uptable（LUT4）capableofimplementinganycombinationallogicfunctionofuptofourinputs，regardlessofcomplexityA‘D’-typeflip-flopwithanoptionalclock-enableandset/resetcontrol

Fastcarrylogicacceleratesarithmeticfunctions：adders，subtracters，comparators，andcounters.Commonclockinputwithpolaritycontrol，clock-enableinput，andoptionalset/resetcontrolinputtothePLBissharedamongalleightLogicCells

Two-port，4KbitRAMblocks（RAM4K）256x16defaultconfiguration;selectabledatawidthusingprogrammablelogicresourcesSimultaneousreadandwriteaccess;idealforFIFOmemoryanddatabufferingapplicationsRAMcontentspre-loadableduringconfiguration

FourI/Obankswithindependentsupplyvoltage，multipleProgrammableInput/Output（PIO）blocks

LVCMOSI/OstandardsandLVDSoutputssupportedinallbanks

I/OBank3supportsadditionalLVDS，andSubLVDSI/OstandardsOneortwoPhase-LockedLoops（PLL）

Verylowpower

ClockmultiplicationanddivisionPhaseshiftinginfixed90°incrementsStaticordynamicphaseshiftingProgrammableinterconnectionsbetweenallprogrammablelogicfunctions

Eightdedicatedlow-skew，high-fanoutclockdistributionnetworksiCE40HX系列主要特性：图1.iCE40HX系列架构图和特性iCE40HX超低功耗可编程逻辑系列主要产品和特性：TheHX-SeriesoftheiCE40™“LosAngeles”mobileFPGA™familyisidealfortabletapplications.Designersofhandheld，battery-basedconsumerproductshavelongawaitedaprogrammablelogicsolutionthatdeliversdesignflexibilityandfasttime-to-marketbenefitscoupledwithfeaturesthataddresstheirpower，logiccapacity，cost，andsmallformfactorrequirements.Thissolution，previouslyunattainablebyotherFPGAsuppliers，isnowprovidedbyLattice’sultra-lowpowermobileFPGAdevices.UtilizingthemobileFPGAplatform，mobiledesignerscanquicklybringnewfeaturesandcustomfunctionalitytomarketwiththeirveryownCustomMobileDevice.DesignerscanachievethisbyeitherusingstateoftheartdevelopmentsoftwareorbyutilizingLattice’sdesignservices.KeyFeaturesIdealforsensormanagementfunctionsincludinginterruptfiltering，interruptaggregation，autopollingBatteryinsertionandaudioinsertiondetectionwithhighspeedcomparatorsSupportMIPISLIMbusInterfaceHighspeedLVDSchannelsupto525MbpsperchannelHighdefinitionvideosupport：HD720p@60Hz，HD1080p@30HzSupportsMIPIDBIandMIPIDPIvideointerfacestandardsHighSpeedUSB2.0hostanddevicecontrollerssupportingULPIandUTMIinterfacesIdealfor3DsolutionsPCBfriendlyfootprintpackagesFabricatedonadvanced40nmstandardCMOSprocess50%fasterthaniCE65™devicesUltra-lowpowerconsumptionUltra-smallfootprintpackagesWorld’sfirst2.5x2.5mm，0.4mmpitchballgridarray2Xlogiccapacitypermm2overiCE65Upto2phase-lockedloopssupportingdualoutputsFlexibleblockRAMiCEblink40iCE40HX1K评估板ThisguidedescribeshowtobeginusingtheiCEblink40EvaluationKit，aneasy-to-useplatformforrapidlyprototyp-ingdesignsusingtheiCE40mobileFPGA™。iCEblink40iCE40HX1K评估板主要特性：•High-performance，low-poweriCE40HX1KmobileFPGA•USBprogramming，debugging，virtualI/Ofunctions，andpowersupply•FouruserLEDs•Fourcapacitive-touchbuttons•3.3MHzclocksource•1MbitSPIserialconfigurationPROM•SupportedbyLatticeiCEcube2™designsoftware•68LVCMOS/LVTTL（3.3V）digitalI/Oconnectionson0.1”th