组合逻辑电路的设计和分析

组合逻辑电路的设计和分析1概述2编码器3译码器4简单数字显示系统5其它定义：任一时刻的输出仅仅取决于当时的输入，与电路原来的状态无关，这样的数字电路叫做组合逻辑电路。常用组合逻辑电路有以下几种：

〔1〕编码器〔2〕译码器〔3〕比较器〔4〕数据选择器〔5〕三态输出电路〔6〕加法器1概述2编码器2.18-3编码器2.2二－十进制编码器编码器有普通编码器和优先编码器，我们设计一个普通的8-3编码器。

输入信号输出信号使能端口一、外观及功能2.18-3编码器

注：EN为1时编码器工作二、其VHDL程序结构体1实体architecturem2ofbmqisbeginprocess(a)beginifen='1'thencaseaiswhen"00000001"=>Y<="000";when"00000010"=>Y<="001";when"00000100"=>Y<="010";when"00001000"=>Y<="011";when"00010000"=>Y<="100";when"00100000"=>Y<="101";when"01000000"=>Y<="110";when"10000000"=>Y<="111";whenothers=>y<="000";endcase;elsey<="000";endif;endprocess;endm2;结构体25.2.2二－十进制编码器

一、外观及功能二、其VHDL程序libraryieee;useieee.std_logic_1164.all;entitybmqisport(A:instd_logic_vector(9downto0);

B:outstd_logic_vector(3downto0));endbmq;architecturem1ofbmqisbeginB<="0000"whenA="0000000001"else"0001"whenA="0000000010"else“0010"whenA="0000000100"else“0011"whenA="0000001000"else“0100"whenA="0000010000"else“0101"whenA="0000100000"else“0110"whenA="0001000000"else“0111"whenA=“0010000000"else“1000"whenA=“0100000000"else“1001"whenA=“1000000000"else“1111"endm1;结构体实体3译码器3.13-8译码器3.2七段显示码译码器3.13-8译码器一、外观及功能二、其VHDL程序libraryieee;useieee.std_logic_1164.all;entityymqisport(Y:instd_logic_vector(2downto0);EN:instd_logic;A:outstd_logic_vector(7downto0));endymq;architecturem1ofymqisbeginprocess(y)beginifen='1'thencaseyiswhen"000"=>A<="00000001";when"001"=>A<="00000010";when"010"=>A<="00000100";when"011"=>A<="00001000";when"100"=>A<="00010000";when"101"=>A<="00100000";when"110"=>A<="01000000";when"111"=>A<="10000000";whenothers=>A<="11111111";endcase;elseA<="11111111";Endif;endprocess;endm1;3.2七段显示码译码器一、外观及功能二、其VHDL程序Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntityxianisPort(C:instd_logic_vector(3downto0);D:outstd_logic_vector(6downto0));Endxian;

Architecturea1ofxianisBeginD<="0111111"whenC="0000"else--0"0000110"whenC="0001"else--1"1011011"whenC="0010"else--2"1001111"whenC="0011"else--3"1100110"whenC="0100"else--4"1101101"whenC="0101"else--5"1111101"whenC="0110"else--6"0000111"whenC="0111"else--7"1111111"whenC="1000"else--8"1101111"whenC="1001"else--9"0000000";Enda1;结构体实体简单数字显示系统数字键盘显示器显示译码器二十进制编码器Libraryieee;Useieee.std_logic_1164.all;Useeee.std_logic_unsigned.all;EntityshuziisPort(X:instd_logic_vector(9downto0);Y:outstd_logic_vector(6downto0));Endshuzi;ArchitectureaofshuziisSignalZ:std_logic_vector(3downto0);ComponentxianPort(C:instd_logic_vector(3downto0);D:outstd_logic_vector(6downto0));endcomponent;ComponentbmqPort(A:instd_logic_vector(9downto0);B:outstd_logic_vector(3downto0));endcomponent;BeginU1:bmqPortmap(x,z);U2:xianPortmap(z,Y);Enda;U1:bmqPortmap(x,z);U2:xianPortmap(z,Y);例化过程：一、数据选择器5.5其它libraryieee;useieee.std_logic_1164.all;entitymux41isport(A,B,C,D:instd_logic_vector(15downto0);Sel:intd_logic_vector(1downto0);Y:outstd_logic_vector(15downto0));endmux41;architectureFofmux41isbeginwithselselectY<=Awhen"00",Bwhen"01",Cwhen"10",Dwhenothers;endF; 二、八位二进制比较器Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;ENTITYcmpabISPORT(A,B:instd_logic_vector(7downto0);Y1,Y2,Y3:outstd_logic);ENDcmpab;ARCHITECTUREaOFcmpabISBEGINY1<='1'whena=belse'0';--并行语句Y2<='1'whena>belse'0';Y3<='1'whena<belse'0';ENDa;时序逻辑电路的设计和分析2触发器3计数器4分频器5存放器1概述任一时刻的输出不仅取决于当时的输入，而且还取决于电路原来的状态，这样的数字电路叫做时序逻辑电路。常用时序电路设计：

〔1〕JK型、T型和D型触发器〔2〕移位存放器设计〔3〕计数器设计〔4〕分频器设计1概述2触发器2.1D触发器2.2T触发器2.3JK触发器符号特性表2.1D触发器LIBRARYIEEE;USEIEEE.std_logic_1164.all;EntityffDisport(clk,d:instd_logic;q:outstd_logic);EndffD;Architecturebody1offfdisbeginprocess(clk)beginifclk’eventandclk=’1’thenq<=d;endif;endprocess;endbody1;Architecturebody2offfdisbeginprocess(clk,d)beginifrising_edge(clk)thenq<=d;endif;endprocess;endbody2;符号特性表6.2.2T触发器LIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYfftISPORT(Cp,T:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDfft;ARCHITECTUREaOFfftISsignalqn:std_logic;BEGINprocess(cp)beginifcp'eventandcp='1'thenifT=’1’thenqn<=notqn;endif;endif;endprocess;q<=qn;ENDa;符号特性表2.3JK触发器LIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYffJKISPORT(Cp,J,K:INSTD_LOGIC;

q:OUTSTD_LOGIC);END

ffJK;ARCHITECTUREaOFffJKIS

signalqn:std_logic;

Signaltt:std_logic_vector(2downto1)BeginProcess(Cp)begintt<=J&K;ifCp’eventandCp=’1’thencasettiswhen“10〞=>qn<=‘1’;when“01〞=>qn<=‘0’;when“11〞=>qn<=notqn;whenothers=>null;Endcase;Endif;EndProcess;q<=qn;Enda;练习题：在JK触发器的结构体中是否可以用with–select语句。计数器的种类很多。按计数器中的触发器是否同时翻转分类，可以把计数器分为同步式和异步式两种。如果按计数过程中计数器中的数字增减分类，有可以分为加法计数器和减法计数器。可增可减的计数器为可逆计数器。有时也用计数器的计数容量来区分各种不同的计数器，如十进制计数器、二十四进制计数器和六十进制计数器等。一、24进制加法计数器

计数器LIBRARYIeee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYcount24ISPORT(en,clk:INSTD_LOGIC;qa:outSTD_LOGIC_VECTOR(3DOWNTO0);--个位数计数qb:outSTD_LOGIC_VECTOR(1DOWNTO0));--十位数计数ENDcount24;实体结构体ARCHITECTUREa1OFcount24ISBEGINprocess(clk)variabletma:STD_LOGIC_VECTOR(3DOWNTO0);variabletmb:STD_LOGIC_VECTOR(1DOWNTO0);beginifclk'eventandclk='1'thenifen='1'theniftma="1001"thentma:="0000";tmb:=tmb+1;Elsiftmb="10"andtma="0011"thentma:="0000";tmb:="00";elsetma:=tma+1;endif;endif;endif;qa<=tma;qb<=tmb;endprocess;ENDa1;二、60进制加法计数器

LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYcount60ISPORT(en,clk:INSTD_LOGIC;qa:outSTD_LOGIC_VECTOR(3DOWNTO0);--个位数计数qb:outSTD_LOGIC_VECTOR(2DOWNTO0);--十数计数rco:OUTSTD_LOGIC);--计数进位ENDcount60;实体结构体ARCHITECTUREaOFcount60ISBEGINprocess(clk)variabletma:STD_LOGIC_VECTOR(3DOWNTO0);variabletmb:STD_LOGIC_VECTOR(2DOWNTO0);beginifclk'eventandclk='1'thenifen='1'thenrco<=tmb(0)andtmb(2)andtma(0)andtma(3)anden;iftma="1001"thentma:="0000";iftmb=“101〞thentmb:=“000〞;elsetmb:=tmb+1;endif;elsetma:=tma+1;endif;endif;endif;qa<=tma;qb<=tmb;endprocess;ENDa;结论:该计数器为十进制加计数器4分频器〔加法4MHz-1hz分频器〕状态图时序图10000100110<1>一个3bits的计数器，它所能计数的范围为0~7〔=23-1〕。同理，nbits的计数器所能计数范围为0~2n-1。<2>Q0、Q1、Q2的波形频率分别为时钟脉冲信号Clk的1/2、1/4、1/8，由此可以知道，nbits的计数器可获得的最低分频频率为时钟脉冲信号Clk的1/2n。<3>对于4MHz频率信号，假设作为加法计数器电路的时钟脉冲信号Clk，那么电路