电子设计自动化(EDA)-数字时钟程序模块(LED数码管显示)-实验报告

PAGEPAGE8电子设计自动化(EDA)—数字时钟LED数码管显示二、实验内容和实验目的1．6个数码管动态扫描显示驱动2．按键模式选择(时\分\秒)与闹钟(时\分)调整控制,3．用硬件描述语言(或混合原理图)设计时、分、秒计数器模块、闹钟模块、按键控制状态机模块、动态扫描显示驱动模块、顶层模块。要求使用实验箱左下角的6个动态数码管(DS6A~DS1A)显示时、分、秒；要求模式按键和调整按键信号都取自经过防抖处理后的按键跳线插孔。实验目的： 1）学会看硬件原理图，2）掌握FPGA硬件开发的基本技能3）培养EDA综合分析、综合设计的能力三、实验步骤、实现方法(或设计思想)及实验结果主要设备:1）PC机，2）硬件实验箱，3）QuartusII软件开发平台。1．打开QuartusII，连接实验箱上的相关硬件资源，如下图1所示。2．建立新文件，选择文本类型或原理图类型。3．编写程序。4．编译5．仿真，加载程序到芯片，观察硬件输出结果(数码管显示)6．结果正确则完成。若结果不正确，则修改程序，再编译，直到正确。模24计数器模块LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYcount24ISPORT(clk,en:INSTD_LOGIC; cout:OUTSTD_LOGIC; hh,hl:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDcount24;ARCHITECTUREarcOFcount24ISSIGNALa,b:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(clk,en)BEGINhh<=a;hl<=b;IF(clk'EVENTANDclk='1')THEN IF(en='1')THEN IF(a="0010"ANDb="0011")THEN a<="0000"; b<="0000"; ELSEIF(b="1001")THEN a<=a+'1'; b<="0000"; ELSEb<=b+'1'; ENDIF; ENDIF; IF(a="0010"ANDb="0010")THEN cout<='1'; ELSEcout<='0'; ENDIF;ENDIF;ENDIF;ENDPROCESS;ENDarc;模60计数器模块LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYcount60ISPORT(clk,en:INSTD_LOGIC; cout:OUTSTD_LOGIC; hh,hl:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDcount60;ARCHITECTUREarcOFcount60ISSIGNALa,b:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALsout:STD_LOGIC;BEGINPROCESS(clk)BEGINhh<=a;hl<=b;IF(clk'EVENTANDclk='1')THEN IF(en='1')THEN IF(a="0101"ANDb="1001")THEN a<="0000"; b<="0000"; ELSEIF(b="1001")THEN a<=a+'1'; b<="0000"; ELSEb<=b+'1'; ENDIF; ENDIF;ENDIF;ENDIF;ENDPROCESS;sout<='1'WHENa="0101"ANDb="1001"ELSE'0';cout<=soutANDen;ENDarc;4-7显示译码模块LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYsegment4to7ISPORT(s:INSTD_LOGIC_VECTOR(3DOWNTO0); a,b,c,d,e,f,g:OUTSTD_LOGIC);ENDsegment4to7;ARCHITECTUREarcOFsegment4to7ISSIGNALy:STD_LOGIC_VECTOR(6DOWNTO0);BEGINa<=y(6);b<=y(5);c<=y(4);d<=y(3);e<=y(2);f<=y(1);g<=y(0);PROCESS(s)BEGINCASEsISWHEN"0000"=>y<="1111110";WHEN"0001"=>y<="0110000";WHEN"0010"=>y<="1101101";WHEN"0011"=>y<="1111001";WHEN"0100"=>y<="0110011";WHEN"0101"=>y<="1011011";WHEN"0110"=>y<="1011111";WHEN"0111"=>y<="1110000";WHEN"1000"=>y<="1111111";WHEN"1001"=>y<="1111011";WHENOTHERS=>y<="0000000";ENDCASE;ENDPROCESS;ENDarc;带闹钟控制模块LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmode_adjust_with_alarmISPORT(adjust,mode,clk1hz:INSTD_LOGIC; clkh,enh,clkm,enm,clks,enha:OUTSTD_LOGIC; clkh_a,clkm_a:OUTSTD_LOGIC; mode_ss:OUTSTD_LOGIC_VECTOR(2DOWNTO0));ENDmode_adjust_with_alarm;ARCHITECTUREarcOFmode_adjust_with_alarmISTYPEmystateIS(s0,s1,s2,s3,s4,s5);SIGNALc_state,next_state:mystate;BEGINPROCESS(c_state)BEGIN CASEc_stateISWHENs0=>next_state<=s1;clkh<=clk1hz;clkm<=clk1hz;clks<=clk1hz; enh<='0';enm<='0';enha<='0';clkh_a<='0';clkm_a<='0';mode_ss<="000";WHENs1=>next_state<=s2;clkh<=adjust; clkm<='0'; clks<='0'; enh<='1';enm<='0';enha<='0';clkh_a<='0';clkm_a<='0'; mode_ss<="001";WHENs2=>next_state<=s3;clkh<='0'; clkm<=adjust; clks<='0'; enh<='0';enm<='1';enha<='0';clkh_a<='0';clkm_a<='0'; mode_ss<="010";WHENs3=>next_state<=s4;clkh<='0'; clkm<='0'; clks<=adjust; enh<='0';enm<='0';enha<='0'; clkh_a<='0'; clkm_a<='0'; mode_ss<="011";WHENs4=>next_state<=s5;clkh<=clk1hz;clkm<=clk1hz;clks<=clk1hz; enh<='0';enm<='0';enha<='1';clkh_a<=adjust;clkm_a<='0'; mode_ss<="100";WHENs5=>next_state<=s0;clkh<=clk1hz;clkm<=clk1hz;clks<=clk1hz; enh<='0';enm<='0';enha<='0';clkh_a<='0';clkm_a<=adjust; mode_ss<="101"; ENDCASE;ENDPROCESS;PROCESS(mode)BEGINIF(mode'EVENTANDmode='1')THEN c_state<=next_state;ENDIF;ENDPROCESS;ENDarc;扫描模块LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYscanISPORT(clk256hz:INSTD_LOGIC;ss:OUTSTD_LOGIC_VECTOR(2DOWNTO0));ENDscan;ARCHITECTUREarcOFscanISTYPEmystateIS(s0,s1,s2,s3,s4,s5);SIGNALc_state,next_state:mystate;BEGINPROCESS(c_state)BEGINCASEc_stateISWHENs0=>next_state<=s1;ss<="010";WHENs1=>next_state<=s2;ss<="011";WHENs2=>next_state<=s3;ss<="100";WHENs3=>next_state<=s4;ss<="101";WHENs4=>next_state<=s5;ss<="110";WHENs5=>next_state<=s0;ss<="111"; ENDCASE;ENDPROCESS;PROCESS(clk256hz)BEGINIF(clk256hz'EVENTANDclk256hz='1')THEN c_state<=next_state;ENDIF;ENDPROCESS;ENDarc;复用模块LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmuxISPORT(hh,hl,mh,ml,sh,sl,hha,hla,mha,mla:INSTD_LOGIC_VECTOR(3DOWNTO0);ss,mode_ss:INSTD_LOGIC_VECTOR(2DOWNTO0);y:OUTSTD_LOGIC_VECTOR(3DOWNTO0);alarm:OUTSTD_LOGIC);ENDmux;ARCHITECTUREarcOFmuxISSIGNALa,hhtmp,hltmp,mhtmp,mltmp,shtmp,sltmp:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(mode_ss)BEGIN CASEmode_ssISWHEN"000"=>hhtmp<=hh;hltmp<=hl;mhtmp<=mh;mltmp<=ml;shtmp<=sh;sltmp<=sl;WHEN"001"=>hhtmp<=hh;hltmp<=hl;mhtmp<=mh;mltmp<=ml;shtmp<=sh;sltmp<=sl;WHEN"010"=>hhtmp<=hh;hltmp<=hl;mhtmp<=mh;mltmp<=ml;shtmp<=sh;sltmp<=sl;WHEN"011"=>hhtmp<=hh;hltmp<=hl;mhtmp<=mh;mltmp<=ml;shtmp<=sh;sltmp<=sl;WHEN"100"=>hhtmp<=hha;hltmp<=hla;mhtmp<=mha;mltmp<=mla;shtmp<=sh;sltmp<=sl;WHEN"101"=>hhtmp<=hha;hltmp<=hla;mhtmp<=mha;mltmp<=mla;shtmp<=sh;sltmp<=sl;WHENOTHERS=>hhtmp<="0000";hltmp<="0000";mhtmp<="0000";mltmp<="0000";shtmp<="0000";sltmp<="0000";ENDCASE;ENDPROCESS;PROCESS(ss)BEGINCASEssISWHEN"010"=>a<=hhtmp;WHEN"011"=>a<=hltmp;WHEN"100"=>a<=mhtmp;WHEN"101"=>a<=mltmp;WHEN"110"=>a<=shtmp;WHEN"111"=>a<=sltmp; WHENOTHERS=>a<="0000";ENDCASE;y<=a;ENDPROCESS;alarm<='1'WHEN((hh=hha)AND(hl=hla)AND(mh=mha)AND(ml=mla))ELSE'0';ENDarc;闪烁模块LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYblink_controlISPORT(ss,mode_ss:INSTD_LOGIC_VECTOR(2DOWNTO0);blink_en:OUTSTD_LOGIC);ENDblink_control;ARCHITECTUREarcOFblink_controlISBEGINPROCESS(ss,mode_ss)BEGINIF(ss="010"ANDmode_ss="001")THENblink_en<='1';ELSIF(ss="011"ANDmode_ss="001")THENblink_en<='1';ELSIF(ss="100"ANDmode_ss="010")THENblink_en<='1';ELSIF(ss="101"ANDmode_ss="010")THENblink_en<='1';ELSIF(ss="110"ANDmode_ss="011")THENblink_en<='1';ELSIF(ss="111"ANDmode_ss="011")THENblink_en<='1';ELSIF(ss="010"ANDmode_ss="100")THENblink_en<='1';ELSIF(ss="011"ANDmode_ss="100")THENblink_en<='1';ELSIF(ss="100"ANDmode_ss="101")THENblink_en<='1';ELSIF(ss="101"ANDmode_ss="101")THENblink_en<='1';ELSEblink_en<='0';ENDIF;ENDPROCESS;ENDarc;Top文件LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYdesign3ISPORT(mode,adjust,clk1hz,clk2hz,clk256hz,clk1khz:INSTD_LOGIC;alarm,a,b,c,d,e,f,g:OUTSTD_LOGIC;ss:OUTSTD_LOGIC_VECTOR(2DOWNTO0));ENDdesign3;ARCHITECTUREarcOFdesign3ISCOMPONENTmode_adjust_with_alarmPORT(adjust,mode,clk1hz:INSTD_LOGIC; clkh,enh,clkm,enm,clks,enha:OUTSTD_LOGIC; clkh_a,clkm_a:OUTSTD_LOGIC; mode_ss:OUTSTD_LOGIC_VECTOR(2DOWNTO0));ENDCOMPONENT;COMPONENTscanPORT(clk256hz:INSTD_LOGIC;ss:OUTSTD_LOGIC_VECTOR(2DOWNTO0));ENDCOMPONENT;COMPONENTsegment4to7PORT(s:INSTD_LOGIC_VECTOR(3DOWNTO0);a,b,c,d,e,f,g:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTmuxPORT(hh,hl,mh,ml,sh,sl,hha,hla,mha,mla:INSTD_LOGIC_VECTOR(3DOWNTO0);ss,mode_ss:INSTD_LOGIC_VECTOR(2DOWNTO0);y:OUTSTD_LOGIC_VECTOR(3DOWNTO0);alarm:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTss,mode_ss:INSTD_LOGIC_VECTOR(2DOWNTO0);blink_en:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTcount24PORT( clk,en:INSTD_LOGIC; cout:OUTSTD_LOGIC; hh,hl:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCOMPONENT;COMPONENTcount60PORT( clk,en:INSTD_LOGIC;cout:OUTSTD_LOGIC;hh,hl:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCOMPONENT;SIGNALclkh,enh,clkm,enm,clks,clkh_a,clkm_a,coutm,couts,coutm_en,couts_en,cout,vcc,coutma_en,coutma,alarm1,blink_en,blink_tmp,enha:STD_LOGIC;SIGNAL mode_ss,ss1:STD_LOGIC_VECTOR(2DOWNTO0);SIGNALhh,hl,mh,ml,sh,sl,hha,hla,mha,mla,y,i:STD_LOGIC_VECTOR(3DOWNTO0);BEGINvcc<='1';coutm_en<=enhORcoutm;couts_en<=enmORcouts;coutma_en<=enhaORcoutma;